MC68HC711D3CFN2 Freescale Semiconductor, MC68HC711D3CFN2 Datasheet - Page 27

• Manufacturer Part Number: MC68HC711D3CFN2
• Description: IC MCU 2MHZ 4K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Freescale Semiconductor
$001C
$001D
$001A
$001B
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
Addr.
Timer Output Compare Register 3
Timer Output Compare Register 3
Timer Output Compare Register 4
Timer Output Compare Register 4
Output Compare 5 Register High
Output Compare 5 Register Low
Timer Interrupt Mask 1 Register
Timer Interrupt Mask 2 Register
Timer Interrupt Flag 1 Register
Timer Interrupt Flag 2 Register
Register Name
Timer Control 1 Register
Timer Control Register 2
Timer Input Capture 4/
Timer Input Capture 4/
Figure 2-2. Register and Control Bit Assignments (Sheet 3 of 5)
See page 92.
See page 92.
See page 92.
See page 92.
See page 90.
See page 90.
See page 95.
See page 89.
See page 95.
See page 96.
See page 96.
See page 97.
High (TOC3)
High (TOC4)
Low (TOC3)
Low (TOC4)
(TMSK1)
(TMSK2)
(TI4/O5)
(TI4/O5)
(TCTL1)
(TCTL2)
(TFLG1)
(TFLG2)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
MC68HC711D3 Data Sheet, Rev. 2.1
EDG4B
Bit 15
Bit 15
Bit 15
OC1F
OC1I
Bit 7
OM2
Bit 7
Bit 7
Bit 7
TOF
TOI
1
1
1
1
1
1
0
0
0
0
0
0
= Unimplemented
EDG4A
OC2F
Bit 14
Bit 14
Bit 14
OC2I
RTIF
Bit 6
Bit 6
Bit 6
OL2
RTII
6
1
1
1
1
1
1
0
0
0
0
0
0
EDG1B
PAOVF
PAOVI
OC3F
Bit 13
Bit 13
Bit 13
OC3I
OM3
Bit 5
Bit 5
Bit 5
5
1
1
1
1
1
1
0
0
0
0
0
0
EDG1A
OC4F
Bit 12
Bit 12
Bit 12
OC4I
PAIF
Bit 4
Bit 4
Bit 4
OL3
PAII
R
4
1
1
1
1
1
1
0
0
0
0
0
0
= Reserved
EDG2B
I4/O5F
I4/O5I
Bit 11
Bit 11
Bit 11
OM4
Bit 3
Bit 3
Bit 3
3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
EDG2A
Bit 10
Bit 10
Bit 10
IC1F
Bit 2
Bit 2
Bit 2
OL4
IC1I
2
1
1
1
1
1
1
0
0
0
0
0
0
0
0
U = Unaffected
EDG3B
OM5
IC2F
Bit 1
Bit 1
Bit 9
Bit 1
Bit 9
Bit 9
IC2I
PR1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Memory Map
EDG3A
Bit 0
IC3F
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
PR0
OL5
IC3I
1
1
1
1
1
1
0
0
0
0
0
0
0
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