MC68HC711D3CFN2 Freescale Semiconductor, MC68HC711D3CFN2 Datasheet - Page 69

• Manufacturer Part Number: MC68HC711D3CFN2
• Description: IC MCU 2MHZ 4K OTP 44-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711D3CFN2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 26
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

6.6 SCI Error Detection
Three error conditions can occur during generation of SCI system interrupts:
Three bits (OR, NF, and FE) in the serial communications status register (SCSR) indicate if one of these
error conditions exists. The overrun error (OR) bit is set when the next byte is ready to be transferred from
the receive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When an overrun
error occurs, the data that caused the overrun is lost and the data that was already in SCDR is not
disturbed. The OR is cleared when the SCSR is read (with OR set), followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and stop bits.
The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is read (with FE
equal to 1) followed by a read of the SCDR.
When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is set at
the same time as the RDRF. If the byte received causes both framing and overrun errors, the processor
only recognizes the overrun error. The framing error flag inhibits further transfer of data into the SCDR
until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of
the SCDR.
6.7 SCI Registers
This subsection describes the five addressable registers in the SCI.
6.7.1 SCI Data Register
The SCI data register (SCDR) is a parallel register that performs two functions. It is the receive data
register when it is read, and the transmit data register when it is written. Reads access the receive data
buffer and writes access the transmit data buffer. Receive and transmit are double buffered.
Freescale Semiconductor
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Serial communications data register (SCDR) overrun
Received bit noise
Framing
Address:
Reset:
Read:
Write:
$002F
R7/T7
Bit 7
R6/T6
Figure 6-3. SCI Data Register (SCDR)
6
MC68HC711D3 Data Sheet, Rev. 2.1
R5/T5
5
Unaffected by reset
R4/T4
4
R3/T3
3
R2/T2
2
R1/T1
1
R0/T0
Bit 0
SCI Error Detection
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