COP8SGR7HLQ8 National Semiconductor, COP8SGR7HLQ8 Datasheet - Page 18

• Manufacturer Part Number: COP8SGR7HLQ8
• Description: IC MCU OTP 8BIT 32K 2-COMP 44LLP
• Manufacturer: National Semiconductor
• Series: COP8™ 8SGr

Specifications of COP8SGR7HLQ8

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 15MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: EPROM, UV
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LLP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: COP8SGR7HLQ8TR

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5.0 Functional Description
Bit 0
5.6 USER STORAGE SPACE IN EPROM
The ECON register is outside of the normal address range of
the ROM and can not be accessed by the executing soft-
ware.
The COP8 assembler defines a special ROM section type,
CONF, into which the ECON may be coded. Both ECON and
User Data are programmed automatically by programmers
that are certified by National.
The following examples illustrate the declaration of ECON
and the User information.
Syntax:
[label:] .sect
Example: The following sets a value in the ECON register
and User Identification for a COP8SGR728M7. The ECON
bit values shown select options: Power-on enabled, Security
disabled, Crystal oscillator with on-chip bias disabled,
WATCHDOG enabled and HALT mode enabled.
5.7 OTP SECURITY
The device has a security feature that, when enabled, pre-
vents external reading of the OTP program memory. The
security bit in the ECON register determines, whether secu-
rity is enabled or disabled. If the security feature is disabled,
the contents of the internal EPROM may be read.
If the security feature is enabled, then any attempt to
externally read the contents of the EPROM will result in
the value FF Hex being read from all program locations
Under no circumstances can a secured part be read. In
addition, with the security feature enabled, the write opera-
tion to the EPROM program memory and ECON register is
inhibited. The ECON register is readable regardless of the
state of the security bit. The security bit, when set, cannot
be erased, even in windowed packages. If the security bit
is set in a device in a windowed package, that device may be
erased but will not be further programmable.
If security is being used, it is recommended that all other bits
in the ECON register be programmed first. Then the security
bit can be programmed.
5.8 ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that era-
sure begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (Å). It should be
noted that sunlight and certain types of fluorescent lamps
have wavelengths in the 3000Å - 4000Å range.
After programming, opaque labels should be placed over the
window of windowed devices to prevent unintentional era-
sure. Covering the window will also prevent temporary func-
tional failure due to the generation of photo currents.
.sect
.db
.db
.endsect
= 0
= 1
= 0
econ, conf
0x55
'my v1.00' ;user data declaration
.db
.db
.endsect
programmed to 0 for all other applications.
Enable full port F capability.
HALT mode disabled.
HALT mode enabled.
econ, conf
value
<user information>
;por, xtal, wd, halt
; up to 8 bytes
;1 byte,
;configures options
(Continued)
18
The recommended erasure procedure for windowed devices
is exposure to short wave ultraviolet light which has a wave-
length of 2537 Angstroms (Å). The integrated dose (i.e. UV
intensity X exposure time) for erasure should be a minimum
of 15W-sec/cm
5.9 RESET
The devices are initialized when the RESET pin is pulled low
or the On-chip Power-On Reset is enabled.
The following occurs upon initialization:
Port L: TRI-STATE (High Impedance Input)
Port C: TRI-STATE (High Impedance Input)
Port G: TRI-STATE (High Impedance Input)
Port F: TRI-STATE (High Impedance Input)
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
T2CNTRL: CLEARED
T3CNTRL: CLEARED
Accumulator, Timer 1, Timer 2 and Timer 3:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
S Register: CLEARED
RAM:
USART:
COMPARATORS:
WATCHDOG (if enabled):
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET with crystal clock option
(power already applied)
UNAFFECTED after RESET with R/C clock option
(power already applied)
RANDOM after RESET at power-on
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
CMPSL; CLEARED
2
.
FIGURE 8. Reset Logic
10131713