COP8SGR7HLQ8 National Semiconductor, COP8SGR7HLQ8 Datasheet - Page 44

• Manufacturer Part Number: COP8SGR7HLQ8
• Description: IC MCU OTP 8BIT 32K 2-COMP 44LLP
• Manufacturer: National Semiconductor
• Series: COP8™ 8SGr

Specifications of COP8SGR7HLQ8

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 15MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: EPROM, UV
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LLP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: COP8SGR7HLQ8TR

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12.0 MICROWIRE/PLUS
12.1.2 MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bits in the Port G configuration
register. Table 11 summarizes the settings required to enter
the Slave mode of operation.
This table assumes that the control flag MSEL is set.
SK Phase
Config. Bit
Alternate
Alternate
G4 (SO)
Normal
Normal
TABLE 11. MICROWIRE/PLUS Mode Settings
1
0
1
0
FIGURE 29. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low
Config. Bit
G5 (SK)
1
1
0
0
G6 (SKSEL)
Config. Bit
TABLE 12. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase
STATE
STATE
0
1
0
1
Fun.
TRI-
TRI-
SO
SO
G4
Port G
Fun.
Ext.
Ext.
G5
Int.
SK
Int.
SK
SK
SK
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Master
MICROWIRE/PLUS
Slave
MICROWIRE/PLUS
Slave
(Continued)
G5 Data
Operation
Bit
0
0
1
1
SO Clocked Out On:
SK Falling Edge
SK Falling Edge
44
SK Rising Edge
SK Rising Edge
The user must set the BUSY flag immediately upon entering
the Slave mode. This ensures that all data bits sent by the
Master is shifted properly. After eight clock pulses the BUSY
flag is clear, the shift clock is stopped, and the sequence
may be repeated.
12.1.3 Alternate SK Phase Operation and SK Idle P
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK idle polarity can be either high or low.
The polarity is selected by bit 5 of Port G data register. In the
normal mode data is shifted in on the rising edge of the SK
clock and the data is shifted out on the falling edge of the SK
clock. In the alternate SK phase operation, data is shifted in
on the falling edge of the SK clock and shifted out on the
rising edge of the SK clock. Bit 6 of Port G configuration
register selects the SK edge.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alter-
nate SK clock. The SKSEL is mapped into the G6 configu-
ration bit. The SKSEL flag will power up in the reset condi-
tion, selecting the normal SK signal.
SI Sampled On:
SK Falling Edge
SK Falling Edge
SK Rising Edge
SK Rising Edge
10131733
SK Idle
Phase
High
High
Low
Low