COP8SGR7HLQ8 National Semiconductor, COP8SGR7HLQ8 Datasheet - Page 37

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COP8SGR7HLQ8

Manufacturer Part Number
COP8SGR7HLQ8
Description
IC MCU OTP 8BIT 32K 2-COMP 44LLP
Manufacturer
National Semiconductor
Series
COP8™ 8SGr
Datasheet

Specifications of COP8SGR7HLQ8

Core Processor
COP8
Core Size
8-Bit
Speed
15MHz
Connectivity
Microwire/Plus (SPI), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
40
Program Memory Size
32KB (32K x 8)
Program Memory Type
EPROM, UV
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LLP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
COP8SGR7HLQ8TR
10.0 Interrupts
10.3.1 VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active
interrupt is software trap, than E0 is generated. This number
replaces the lower byte of the PC. The upper byte of the PC
(Continued)
FIGURE 26. VIS Operation
37
remains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration
ranking. This vector is read from program memory and
placed into the PC which is now pointed to the 1st instruction
of the service routine of the active interrupt with the highest
arbitration ranking.
Figure 26 illustrates the different steps performed by the VIS
instruction. Figure 27 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
10131729
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