MC68HC908GR16CFJ Freescale Semiconductor, MC68HC908GR16CFJ Datasheet - Page 239

• Manufacturer Part Number: MC68HC908GR16CFJ
• Description: IC MCU 16K FLASH 8MHZ SPI 32LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR16CFJ

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.2.1.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
19.2.1.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
19.2.1.4 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary
register (BRKAR).
19.2.2 Break Module Registers
These registers control and monitor operation of the break module:
19.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
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This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
1 = Break address match
0 = No break address match
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
Address: $FE0B
Reset:
Read:
Write:
Figure 19-3. Break Status and Control Register (BRKSCR)
BRKE
Bit 7
0
= Unimplemented
BRKA
6
0
MC68HC908GR16 Data Sheet, Rev. 5.0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Break Module (BRK)
Bit 0
0
0
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