MC68HC908MR8CP Freescale Semiconductor, MC68HC908MR8CP Datasheet - Page 121

• Manufacturer Part Number: MC68HC908MR8CP
• Description: IC MCU 8K FLASH 8MHZ PWM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.4.2.5 Special Programming Exceptions
8.4.3 Base Clock Selector Circuit
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
The programming method described in
does not account for possible exceptions. A value of 0 for N or L is
meaningless when used in the equations given. To account for these
exceptions:
This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in state.
The output of the transition control circuit is then divided by two to correct
the duty cycle. Therefore, the bus clock frequency, which is one-half of
the base clock frequency, is one-fourth the frequency of the selected
clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a 0.
This value would set up a condition inconsistent with the operation of the
PLL, so that the PLL would be disabled and the crystal clock would be
forced as the source of the base clock.
•
•
A 0 value for N is interpreted exactly the same as a value of 1.
A 0 value for L disables the PLL and prevents its selection as the
source for the base clock. See
Circuit.
Clock Generator Module (CGM)
8.4.3 Base Clock Selector
8.4.2.4 Programming the PLL
Clock Generator Module (CGM)
Functional Description
Technical Data
121