MC68HC908MR8CP Freescale Semiconductor, MC68HC908MR8CP Datasheet - Page 135

• Manufacturer Part Number: MC68HC908MR8CP
• Description: IC MCU 8K FLASH 8MHZ PWM 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.11.2 Parametric Influences on Reaction Time
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is also under user control via the choice of
crystal frequency, f
•
•
Acquisition time, t
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance, ∆
Acquisition time is based on an initial frequency error,
(f
bandwidth control mode (see
Bandwidth
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance, ∆
time is based on an initial frequency error, (f
not more than ± 100 percent. In automatic bandwidth control
mode, lock time expires when the LOCK bit becomes set in the
PLL bandwidth control register (PBWC). See
Automatic PLL Bandwidth
DES
Clock Generator Module (CGM)
– f
ORIG
Lock
Modes), acquisition time expires when the ACQ bit
)/f
XCLK
DES
, is the time the PLL takes to reduce the error
ACQ
.
, of not more than ±100 percent. In automatic
, is the time the PLL takes to reduce the error
RDV
. This frequency is the input to the phase
Modes.
8.4.2.3 Manual and Automatic PLL
Acquisition/Lock Time Specifications
Clock Generator Module (CGM)
DES
8.4.2.3 Manual and
–f
ORIG
Technical Data
)/f
Lock
DES
. Lock
TRK
, of
135
.