HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 142

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Table 8.5
Note: * Sampled in the address/data multiplexed I/O space.
Bits 7–0—Single-Mode DMA Memory Write Wait State Control (DWW7–DWW0): DWW7–
DWW0 determine the number of states in single-mode DMA memory write cycles for each area
and whether or not to sample the WAIT signal. Bits DWW7–DWW0 correspond to areas 7–0,
respectively. If a bit is cleared to 0, the WAIT signal is not sampled during the single-mode DMA
memory write cycle for the corresponding area. If it is set to 1, sampling takes place.
The number of states for areas accesses based on bit settings is the same as indicated for single-
mode DMA memory read cycles. See bits 15–8, Wait State Control During Single-Mode DMA
Memory Transfer (DRW7–DRW0), for details.
Table 8.6 summarizes single-mode DMA memory write cycle state information.
Rev. 7.00 Jan 31, 2006 page 114 of 658
REJ09B0272-0700
Bits 15–8:
DRW7–DRW0
0
1
Single-Mode DMA Memory Read Cycle States (External Memory Space)
WAIT
WAIT Pin Input
Signal
Not sampled during
single-mode DMA
memory read cycle *
Sampled during
single-mode DMA
memory read cycle
(Initial value)
WAIT
WAIT
External Memory Space
Areas 1, 3–5,7: 1 state, fixed
Areas 0, 2, 6: 1 state +
long wait state
Areas 1, 3–5, 7: 2 states
+ wait states from WAIT
Areas 0, 2, 6: 1 state +
long wait state + wait
state from WAIT
Single-Mode DMA Memory Read Cycle States
(External Memory Space)
DRAM Space
Column address
cycle: 1 state,
fixed (short pitch)
Column address
cycle: 2 states +
wait state from
WAIT (long pitch)
Multiplexed
I/O
4 states +
wait states
from WAIT