HD6417032F20 Renesas Electronics America, HD6417032F20 Datasheet - Page 353

• Manufacturer Part Number: HD6417032F20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1 and G0CMS0): G0CMS1
and G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3–TP0).
Bit 1:
G0CMS1
0
1
11.2.8
TPMR is an eight-bit read/write register that selects between the TPC’s ordinary output and non-
overlap output modes in group units. During non-overlap operation, the output waveform cycle is
set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in
general register A (GRA). The output value then changes on compare matches A and B. For
details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 by a
reset. It is not initialized in standby mode.
Bits 7–4—Reserved: These bits are always read as 1. The write value should always be 1.
Bit 3—Group 3 Non-Overlap Mode (G3NOV): G3NOV selects ordinary or non-overlap mode
for TPC output group 3 (TP15–TP12).
Bit 3: G3NOV
0
1
Bit
Initial value
Read/Write
TPC Output Mode Register (TPMR)
Bit 0:
G0CMS0
0
1
0
1
Description
TPC output group 3 operates normally (output value updated according to
compare match A of the ITU channel selected by TPCR)
TPC output group 3 operates in non-overlap mode (1 output and 0 output can
be performed independently according to compare match A and B of the ITU
channel selected by TPCR)
—
—
7
1
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 0
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 1
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 2
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 3
Description
—
—
6
1
Section 11 Programmable Timing Pattern Controller (TPC)
—
—
5
1
—
—
4
1
Rev. 7.00 Jan 31, 2006 page 325 of 658
G3NOV G2NOV G1NOV G0NOV
R/W
3
0
R/W
2
0
REJ09B0272-0700
R/W
1
0
(Initial value)
(Initial value)
R/W
0
0