MC9S12UF32PB Freescale Semiconductor, MC9S12UF32PB Datasheet
MC9S12UF32PB
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MC9S12UF32PB Summary of contents
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... Industrial: Typically 10 year applications - installed telecom equipment, work stations, servers, etc. These products can also be used for Commercial applications. Automotive: Qualified per automotive industry standard methods. MC9S12UF32 V01.05 Original Release Date: 17 JAN 2002 Revised: 03 Dec 2004 TSPG - 8/16 Bit MCU Design, HKG Freescale Semiconductor, Inc. ...
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... Freescale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Freescale Semiconductor does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Freescale ...
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... Wai-On Law 01.05 03DEC04 Wai-On Law Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Author - Removed all references to XCLKS, since function is removed. - typo - replaced PRU with RPU. - typo - replaced ATAHC with ATA5HC - Removed references to clock monitor, since function is not available ...
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... System on a Chip Guide — 9S12UF32DGV1/D V01.05 4 Freescale Semiconductor ...
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... PB[7:0] / ADDR[7:0] / DATA[7:0] / CFD[7:0] / ATAD[7:0] — Port B I/O Pins . . . . . . .59 2.4.17 PE7 / NOACC — Port E I/O Pin .59 2.4.18 PE6 / MODB / IPIPE1 — Port E I/O Pin .59 2.4.19 PE5 / MODA / IPIPE0 — Port E I/O Pin .59 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 5 ...
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... PS0 / CFCE1 / ATACS0 — Port S I/O Pin .65 2.4.52 PT[3:0] / IOC[3:0]— Port T I/O Pins [3: .66 2.4.53 PU[5:3] / CFA[2:0] / ATADA[2:0] — Port U I/O Pins [5: .66 2.4.54 PU2 / CFREG — Port U I/O Pin .66 2.4.55 PU1 / CFINPACK / ATADMACK — Port U I/O Pin .66 6 Freescale Semiconductor ...
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... PQ5 / SDAT5 / CFA5 / SDCMD / IOC5 — Port Q I/O Pins .72 2.5.31 PQ4 / SDAT4 / CFA4 / ATADMACK / IOC4 — Port Q I/O Pins .72 2.5.32 PQ3 / SDAT3 / CFIORD / ATAIORD — Port Q I/O Pins .72 2.5.33 PQ[2:0] / SDAT[2:0] / CFA[2:0] / ATADA[2:0]— Port Q I/O Pins [2: .72 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 7 ...
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... Security .82 4.4.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.4.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.4.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 4.5.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 4.5.2 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 4.5.3 Run .84 Section 5 Resets and Interrupts 5.1 Overview .85 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.2.1 Vector Table .85 5.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 8 Freescale Semiconductor ...
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... Section 12 Memorystick Host Controller (MSHC) Block Description 12.1 Device-specific information .91 Section 13 Oscillator (OSC) Block Description 13.1 Device-specific information .91 Section 14 Port Integration Module (PIM) Block Description 14.1 Device-specific information .92 Section 15 Serial Communication Interface (SCI) Block Description 15.1 Device-specific information .92 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 9 ...
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... Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 A.1.4 Current Injection .98 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .101 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 A.2 NVM, Flash .109 10 Freescale Semiconductor ...
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... Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 A.4.3 USB PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 A.5 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 A.5.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Appendix B Package Information B.1 General .123 B.2 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 B.3 64-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 11 ...
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... System on a Chip Guide — 9S12UF32DGV1/D V01.05 12 Freescale Semiconductor ...
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... Figure 22-1 Sample schematic with 64-pin LQFP MC9S12UF32 .95 Figure A-1 General External Bus Timing 119 Figure B-1 100-pin LQFP mechanical dimensions (case no. 983 124 Figure B-2 64-pin LQFP mechanical dimensions (case no. 840F 125 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 13 ...
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... System on a Chip Guide — 9S12UF32DGV1/D V01.05 14 Freescale Semiconductor ...
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... NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Table A-10 NVM Reliability Characteristics .111 Table A-11 Voltage Regulator Recommended Load Resistances/Capacitances . . . . . . . . .113 Table A-12 Startup Characteristics .115 Table A-13 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Table A-15 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 15 ...
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... System on a Chip Guide — 9S12UF32DGV1/D V01.05 16 Freescale Semiconductor ...
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... Technology - AT Attachment with Packet Interface - 5 (ATA/ATAPI5),” T13/1321D rev 3, 29 February, 2000, ANSI. • “CF+ and CompactFlash Specification,” rev. 2.0 5/2003, CompactFlash Association. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table 0-1 Document References HCS12 CPU Reference Manual ...
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... Part Number Figure 0-1 provides an ordering number example. MC9S12 UF32 FU Figure 0-1 Order Part Number Coding Table 0-2 lists the part number coding based on the package. Part Number MC9S12UF32PB MC9S12UF32PU 18 Package Option Device Title Controller Family Table 0-2 Part Number Coding ...
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... Flash EEPROM - Internal program/erase voltage generation - Security and Block Protect bits – 3.5K byte RAM NOTES: 1. Not all functions are available simultaneously. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01. The MC9S12UF32 has full 16-bit internal data paths throughout. 19 ...
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... USB 2.0 Serial Interface Engine (USB20SIE) for High Speed and Full Speed operations compatible - Endpoint 0 for Control IN and OUT operation - Endpoint 2 and 3 are configurable for Bulk, ISO or Interrupt IN/OUT operation - Endpoint buffer with programmable size residing in Queue RAM for endpoints 4 and 5 20 Freescale Semiconductor ...
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... The Document for the Memory Stick Host Controller in the 912UF32 will be available to users who have obtained a formal license of Memory Stick from Sony. Memory Stick is a Sony technology. 2. IRQ is not available in 64 pin device. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 1 ...
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... Special Peripheral Mode (Freescale use only) • Each of the above modes of operation can be configured for two Low power sub-modes – Stop Mode – Wait Mode • Secure operation, preventing the unauthorized read and write of the flash memory contents. 22 Freescale Semiconductor ...
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... IPbus runs at 1/2 frequency of S12 core bus, which is controlled by REFDV register of CRG_U module. *Qbus refers to the data transfer channels between IQUE and USB/ATA5HC/CFHC/MSHC/SDHC/SMHC. Figure 1-1 MC9S12UF32 Block Diagram Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 I/O Driver 3.3/5V VDDX VSSX 3 ...
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... SRAM located at $0800 - $0FCF and $1000 - $17CF Unmapped locations in range $0800 - $1BC3 are reserved RAM array (SMRAM3P5K2E) $1BC4 - $1FFF 1084-byte 16-bit SRAM 24 Table 1-1 Device Memory Map Module Size Mapping (Bytes) Register( INITRG 160 256 1 2048 INITEE 5060 INITRM 1084 Freescale Semiconductor ...
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... The figure shows an example of an application memory map with the following register setting. This is not the map out of reset. INITRG = $00 INITRM = $20 INITEE = $11 PPAGE = $3E Figure 1-2 MC9S12UF32 Memory Map (Application Example) Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table 1-1 Device Memory Map EXT VECTORS VECTORS EXPANDED ...
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... Bit Bit 2 0 LSTRE RDWE 0 0 IVIS EMK 0 0 PUPBE 0 0 RDPB Bit 3 Bit 2 Bit RAM11 0 0 REG11 0 0 EE11 0 EXSTR1 EXSTR0 ROMHM ROMON Freescale Semiconductor Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 0 Bit EME PUPAE RDPA ESTR 0 Bit 0 RAMHAL 0 EEON 0 ...
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... Read: reg_sw0 $001C MEMSIZ0 Write: Read: rom_sw1 rom_sw0 $001D MEMSIZ1 Write: $001E - $001E Address Name Read: $001E INTCR Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 INT map (HCS12 Interrupt) Bit 7 Bit 6 Bit 5 Bit WRINT INTE INTC INTA INT8 ...
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... Bit 3 Bit 2 Bit 1 PSEL3 PSEL2 PSEL1 Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit BK0V3 BK0V2 BK0V1 BK1V3 BK1V2 BK1V1 Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit Freescale Semiconductor Bit 0 0 Bit 0 0 Bit 0 0 BK0V0 Bit 8 Bit 0 BK1V0 Bit 8 Bit 0 Bit Bit ...
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... TCNT (lo) Write: Read: $0046 TSCR1 Write: Read: $0047 TTOV Write: Read: $0048 TCTL1 Write: Read: $0049 TCTL2 Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 CRG_U (Clock and Reset Generator) Bit 7 Bit 6 Bit 5 Bit TOUT6 TOUT5 TOUT4 0 RTIF PORF ...
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... EDG0B C3I C2I C1I 0 TCRE PR2 PR1 C3F C2F C1F CLK1 CLK0 PAOVI PAOVF Freescale Semiconductor Bit 0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 ...
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... Address Name Read: $00C8 SCIBDH Write: Read: $00C9 SCIBDL Write: Read: $00CA SCICR1 Write: Read: $00CB SCICR2 Write: Read: $00CC SCISR1 Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 TIM (Timer 16-Bit 8 Channels) Bit 7 Bit 6 Bit 5 Bit 4 Bit ...
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... CBEIF PVIOL ACCERR 0 CMDB6 CMDB5 Bit 3 Bit 2 Bit BRK13 TXDIR Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit 1 FDIV3 FDIV2 FDIV1 NV3 NV2 SEC1 BKSEL1 BKSEL0 FPHS0 FPLDIS FPLS1 0 0 BLANK CMDB2 Freescale Semiconductor Bit 0 RAF Bit 0 0 Bit 0 FDIV0 SEC0 0 FPLS0 0 CMDB0 ...
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... Read: $01C7 HPIO2 (lo) Write: Read: $01C8 HPIO3 (hi) Write: Read: $01C9 HPIO3 (lo) Write: Read: $01CA HPIO4 (hi) Write: Read: $01CB HPIO4 (lo) Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Reserved Bit 7 Bit 6 Bit 5 Bit SMRAM Control Register Bit 7 Bit 6 Bit 5 Bit ...
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... Bit 3 Bit 2 Bit 1 DMA_T0 DMA_TD DMA_TK 0 DMA_TM 0 0 DMA_TH 0 0 DMA_TJ 0 0 DMA_TN UDMA_T2CYCTYP UDMA_TCYC 0 0 UDMA_TDS 0 0 UDMA_TDH UDMA_TDVS 0 0 UDMA_TDVH UDMA_TFS TDMA_TU 0 0 UDMA_TMLI 0 0 UDMA_TAZ UDMA_TENV 0 UDMA_TSR 0 UDMA_TSS UDMA_TRFS UDMA_TRP 0 0 UDMA_TACK 0 0 UDMA_TZAH Freescale Semiconductor Bit 0 0 ...
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... NOTES: 1. These registers are mapped to the registers on an external ATA/ATAPI device, for detail explanation of the #, #r1, #r2, #w, #1,#2 field, please refer to the ATAHC block guide and ATA/ATAPI standards. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 ATA Host Controller (ATA5HC) Bit 7 ...
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... Bit 3 Bit 2 Bit IQUERST Q1DATA Q1DATA 0 BEGPTR BEGPTR 0 ENDPTR ENDPTR Q1SML Q116EN Q1THRU Q1FIF Q1EIF QBASE 0 Q1REQ Q2DATA Q2DATA 0 BEGPTR BEGPTR 0 ENDPTR ENDPTR Q2SML Q216EN Q2THRU Q2FIF Q2EIF QBASE 0 Q2REQ Q3DATA Q3DATA 0 BEGPTR Freescale Semiconductor Bit 0 IQUEEN 0 0 Q1PRST 0 0 Q2PRST 0 ...
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... Write: Read: $022C QC12DSR Write: Read: $022D QC34DSR Write: Read: $022E QCDCT (hi) Write: Read: $022F QCDCT (lo) Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 IQUE (Integrated Queue Module) Bit 7 Bit 6 Bit 5 Bit Q3VIE Q3EIE Q3FIE Q3EN Q3VIF Q3VSF Q3FSF ...
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... PERM1 PPSM3 PPSM2 PPSM1 PTJ2 PTJ1 0 0 PTIJ2 PTIJ1 0 0 DDRJ2 DDRJ1 0 0 RDRJ2 RDRJ1 0 0 PERJ2 PERJ1 Freescale Semiconductor Bit 0 DTHE DTHE 0 Bit 0 PTT0 PTIT0 DDRT0 RDRT0 PERT0 PPST0 0 PTM0 PTIM0 DDRM0 RDRM0 PERM0 PPSM0 0 PTJ0 PTIJ0 DDRJ0 RDRJ0 PERJ0 ...
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... Read: $026C PERR Write: Read: $026D PPSR Write: Read: $026E - Reserved $026F Write: Read: $0270 PTS Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 PIM (Port Integration Module PIM_9UF32) Bit 7 Bit 6 Bit 5 Bit MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP7 ...
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... Bit 3 Bit 2 Bit VCC CD2 CD1 SPKRB CE2B CE1B REGB CFSWAI IEDGE WERRIE TERRIE VSIE RDYIE CHGIE CA6E CA5E CA4E TPS5-TPS0 Freescale Semiconductor Bit 0 PTIS0 DDRS0 RDRS0 PERS0 PPSS0 0 PTU0 PTIU0 DDRU0 RDRU0 PERU0 PPSU0 0 Bit 0 CWAIT CHG 0 COM CDIE 0 0 ...
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... Read: $02A5 MSTDATA (lo) Write: Read: $02A6 MSRDATA (hi) Write: Read: $02A7 MSRDATA (lo) Write: Read: $02A8 MSIC Write: Read: $02A9 MSIS Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 CFHC (Compact Flash Host Controller) Bit 7 Bit 6 Bit 5 Bit 4 BSY 0 TQ HIS ...
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... RDP CDIN CDOUT CDOUTIEN BAF1P DRQ BUSY RBE RBF TBE 0 0 PS2 PS1 Bit 3 Bit 2 Bit PUEN PDEN QIEN CD ECR WRDN RSPTO RD_ECRC WR_ECRC Freescale Semiconductor Bit 0 TFE Bit 0 CNT0 0 SCE RDY RDYIEN CP TBF PS0 0 Bit 0 0 SDEN DTDN RDTO ...
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... SDRSP (hi) Write: Read: $02D9 SDRSP (lo) Write: Read: $02DA SDATA (hi) Write: Read: $02DB SDATA (lo) Write: $02DC - Read: Reserved $02DF Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 SDHC (Secure Digital Host Controller) Bit 7 Bit 6 Bit 5 Bit INIT BUSY MBLK SBMOD ...
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... Bit 3 Bit 2 Bit Bit 3 Bit 2 Bit SPHY PHYRST EPRST EXSPD RWUC SPWR ENUMD 0 URSC URD SOF SETOVR SOFIE SETOVRIE TIMEST 10-8 TIMEST 7-0 CFG ALTINTF 0 UCRSEL 0 EPBSEL0 MAXPSZ EPASET EPCFG EPNUM Freescale Semiconductor Bit 0 0 Bit 0 0 SCSUP 0 SETUP 0 SETUPIE ...
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... UEPCSR5B (hi) Write: Read: $0323 UEPCSR5B (lo) Write: Read: $0324 - Reserved $0337 Write: $0338 - Read: USTB $033F Write: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 USB20D6E2F (Universal Serial Bus 2.0 Device Controller) Bit 7 Bit 6 Bit 5 Bit NINTC1 NAI3C2 NAI1C2 NAI3C1 ...
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... Endpoint Local Buffer Endpoint Local Buffer Table 1-2 Assigned Part ID Numbers Mask Set Number 0L24N 1L79R 0L47S 1L47S Table 1-3 Memory size registers Register name Value MEMSIZ0 MEMSIZ1 Bit 4 Bit 3 Bit 2 Bit Part ID $6300 $6300 $6310 $6311 $12 $80 Freescale Semiconductor Bit 0 0 ...
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... In the 64-pin option, four primary software selectable configurations are available for different end applications. • USB 2.0 to ATA bridge with optional SDHC support • USB 2.0 to SM, SD (MMC) and MS bridge Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 ATA, SM, SD and MS bridge $10 $00 VDDX = 3 ...
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... ATA5HC, SMHC, SDHC, MSHC SCI, TIM SCI pins are routed to PS[5:4] When TIMER is enabled, timer channel pins IOC[7:4] will be available on PQ[7:4] if CA7E, CA6E, CA5E and CA4E in CFSCR2 of CFHC are set to 0. Timer channels IOC[3:0] are not available at pin level. Freescale Semiconductor ...
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... SCD/ACFD09/AATAD09/PP1 23 SCE/ACFD10/AATAD10/PP2 24 SWP/ACFD11/AATA11/PP3 25 SCLE/ACFD12/AATA12/PP4 Note: Not all pin functions are shown in the diagram. Please refer to sections 2-2 and 2-4 for details. Figure 2-1 Pin Assignments in 100-pin LQFP Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 MC9S12UF32 100LQFP PS7/CFRDY/ATAINTQ 75 PS6/CFWE/ATADMARQ 74 PS5/CFIORW/ATAIORW ...
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... Note: Not all pin functions are shown in the diagram. Please refer to sections 2-3 and 2-5 for details. Figure 2-2 Pin Assignments in 64-pin LQFP MC9S12UF32 9 64 LQFP PS7/CFRDY/ATAINTQ/MSSDIO 47 PS6/CFWE/ATADMARQ/CSCLK 46 PS5/TXD 45 PS4/RXD 44 PU0/CFWAIT/ATAIORDY/SCD 43 VDDX 42 VSSX 41 PA7/ADDR15/DATA15/ATAD15/CFD15 40 PA6/ADDR14/DATA14/ATAD14/CFD14/MSBS 39 PA5/ADDR13/DATA13/ATAD13/CFD13 38 PA4/ADDR12/DATA12/ATAD12/CFD12 37 PA3/ADDR11/DATA11/ATAD11/CFD11 36 PA2/ADDR10/DATA10/ATAD10/CFD10 35 PA1/ADDR9/DATA9/ATAD9/CFD9 34 PA0/ADDR8/DATA8/ATAD8/CFD8 33 PB7/ADDR7/DATA7/ATAD7/CFD7/IOC7 Freescale Semiconductor ...
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... DMF — — DMH — — REF3V — — — — PWROFF5V — — PWROFF3V Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table 2-3 100-pin Signal Properties Internal Pull Pin Name Resistor Supply Function Rail 4 CTRL — — — ...
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... Port P I/O Pins; SMHC SCD; Disabled Alternate CFHC, ATA5HC Data lines Port P I/O Pins; SMHC SBSY; Disabled Alternate CFHC, ATA5HC Data lines Port Q I/O Pins; SMHC Data lines, Disabled Alternate CFHC, ATA5HC Data lines Port R I/O Pins; CFHC address Disabled lines Freescale Semiconductor ...
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... CFWAIT ATAIORDY NOTES: 1. This pin must be tied to VSS in Application 2. CFHC module port routing when bit 4 of MODRR is set PJ2 is used as the ROMCTL signal during reset. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Internal Pull Pin Name Resistor Supply Function ...
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... Port A I/O pin; multiplexed address/data; CFHC Data; PUCR Disabled ATA5HC Data; SDHC SDDATA1 signal. Port A I/O pin; multiplexed address/data; CFHC Data; PUCR Disabled ATA5HC Data; SDHC SDDATA0 signal. Port A I/O pin; multiplexed address/data; CFHC Data; PUCR Disabled ATA5HC Data; SDHC SDCLK signal. Freescale Semiconductor ...
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... PJ2 PM4 SBSY CFIOIS16 PM3 SCE CFINPACK PQ7 SDAT7 CFA7 PQ6 SDAT6 CFA6 PQ5 SDAT5 CFA5 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Pin Name Pin Name Supply Function Function Rail 4 5 ATAD8 SDCMD VDDX ATAD[7:0] IOC[7:0] VDDX — ...
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... CFHC CFOE signal; PPST SDHC data; Timer channel; Port T I/O Pins; SMHC SRE PERT/ Disabled signal; CFHC CFREG signal; PPST SDHC data; Timer channel; Port U I/O Pins; CFHC WAIT PERU/ Disabled signal; ATA IORDY signal; SMHC PPSU SCD signal. Freescale Semiconductor ...
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... RPU is an analog input for the USB physical layer module. Refer to USB20D6E2F block guide for further information. 2.4.7 RREF — External bias resistor RREF is an analog input for the USB physical layer module. Refer to USB20D6E2F block guide for further information. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 57 ...
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... REF3V a regulator reference for driving an external NMOS device to provide the system with a regulated 3.3V supply. The feedback path for the REF3V is the VDD3X supply pin. Refer to VREG_U block guide for further information. 2.4.15 PA[7:0] / ADDR[15:8] / DATA[15:8] / CFD[15:8] / ATAD[15:8] — Port A 58 Freescale Semiconductor ...
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... Reference the MISC register (EXSTR[1:0] bits) for more information. In normal expanded narrow mode, the ECLK is available for use in external select decode logic constant speed clock for use in the external application system. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 59 ...
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... MSHC module. While in reset and immediately out of reset the PJ2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide and the MSHC Block Guide for information about pin configurations. 60 Freescale Semiconductor ...
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... PP7 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the MSHC Block Guide for information about pin configurations. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 61 ...
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... CFHC or ATA5HC in place of PA2. While in reset and immediately out of reset PP2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the MSHC Block Guide for information about pin configurations. 62 Freescale Semiconductor ...
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... PR[2] pin is configured as high impedance input pin. Consult the Serial Communication Interface (SCI), the Port Integration Module (PIM) PIM_9UF32 Block Guide and the CFHC Block Guide for information about pin configurations. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 63 ...
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... PS5 becomes the compact flash I/O write pin, CFIOWR. When the CFHC is not enabled, it can be configured as the ATA I/O write pin, ATAIOWR, when the ATA5 host controller (ATA5HC) is enabled. While in reset and immediately out of reset the PS5 pin is configured as a high impedance input pin. 64 Freescale Semiconductor ...
Page 65
... While in reset and immediately out of reset the PS0 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the ATA5HC Block Guide for information about pin configurations. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 65 ...
Page 66
... ATA I/O ready pin, ATAIORDY, when the ATA5 host controller (ATA5HC) is enabled. While in reset and immediately out of reset the PU0 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the ATA5HC Block Guide for information about pin configurations. 66 Freescale Semiconductor ...
Page 67
... DPF is the D+ analog input output line for full speed data communication in the USB physical layer module. This line is also used for D+ termination during high speed operation. Refer to USB20D6E2F block guide for further information. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 67 ...
Page 68
... In single chip mode, this port pin can be configured as MSBS signal for MSHC function, data bus pin for CFHC or ATA5HC. Refer to Table 2-2 for module routing information. For further functional information, do refer to MSHC, CFHC and ATA5HC block guide. 68 Freescale Semiconductor ...
Page 69
... PE4 / ECLK— Port E I/O Pin 4 / E-Clock Output PE4 is a general purpose input or output pin. It can also be configured as the output connection for the internal bus clock (ECLK). ECLK is used to demultiplex the address and data in expanded modes and is Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 69 ...
Page 70
... ROMON bit. This pin can be used as CFCE2 of CFHC module, ATACS1 of ATA5HC module or SWP of SMHC module. Refer to Table 2-2 for module routing information. While in reset and immediately out of reset the PJ2 pin is configured as a high impedance input pin. Consult the Port 70 Freescale Semiconductor ...
Page 71
... PQ7 pin is configured as high impedance input. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the TIM_16B8C Block Guide and the SMHC Block Guide for information about pin configurations. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 71 ...
Page 72
... While in reset and immediately out of reset PQ[2:0] pins are configured as high impedance input pins. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide, the ATA5HC Block Guide and the SMHC Block Guide for information about pin configurations. 72 Freescale Semiconductor ...
Page 73
... TIM_16B8 module, SDDATA0 of SDHC module or SRE of SMHC module. Refer to Table 2-2 for module routing information. While in reset and immediately out of reset the PT0 pin is configured as a high impedance input. Consult the SDHC Block Guide, SMHC Block Guide, CFHC Block Guide, Port Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 73 ...
Page 74
... VREGEN, BKDG and RESET. Internal digital core power generated by internal regulator. External power and ground, supply to pin drivers for Ports and U. External power and ground, supply to pin drivers for Port and T. Internal power and ground for USB PHY generated by internal regulator. Freescale Semiconductor ...
Page 75
... VDDA is 3.3v output for connecting USB pull-up resistor (RPU). NOTE: No load allowed except for bypass capacitors and RPU. VSSA and VSSA1 are ground of USB PHY, which generates the 480bps USB signals. VSSA should also be used for ground of Pierce oscillator crystal. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 75 ...
Page 76
... Oscillator pads EXTAL and XTAL are supplied by internal voltage regulator directly. 2. TEST pin is for factory test only. For normal use, it can be left unconnected. 48 PS7 PS6 46 PS5 45 PS4 44 PU0 43 VDDX 42 VSSX 41 PA7 40 PA6 39 PA5 38 PA4 37 PA3 36 PA2 35 PA1 34 PA0 33 PB7 Freescale Semiconductor ...
Page 77
... CRG_U NOTES: 1. UTMI clock and IQUE clock are fixed 30MHz and 60MHz respectively only when PHY (instead of OSC) is selected as the clock source. See CRG_U Block Guide for details. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 core clock S12_CORE Flash ...
Page 78
... Special Test (Expanded Wide), BDM allowed 1 Emulation Expanded Wide, BDM allowed 0 Normal Single Chip, BDM allowed 1 Normal Expanded Narrow, BDM allowed Special Peripheral; BDM allowed but bus operations would cause bus 0 conflicts (must not be used) 1 Normal Expanded Wide, BDM allowed Freescale Semiconductor ...
Page 79
... PEAR register. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 79 ...
Page 80
... Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output 80 Freescale Semiconductor ...
Page 81
... MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with pull-ups enabled. PE4/ECLK is configured as the ECLK output in this mode. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 81 ...
Page 82
... BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. 4.4 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: 82 Freescale Semiconductor ...
Page 83
... Flash memory space at the appropriate addresses, in the correct order. In addition, in SINGLE CHIP mode the user code stored in the Flash must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 83 ...
Page 84
... So, for example, data can still be transferred from ATA5HC to USB via IQUE. For further power consumption, the peripherals can individually turn off their local clocks. 4.5.3 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. 84 Freescale Semiconductor ...
Page 85
... USB status change $FFD2, $FFD3 USB Setup command related USB set endpoint configuration register $FFD0, $FFD1 $FFCE, $FFCF USB Endpoint 0 IN Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table 5-1 Interrupt Vector Locations CCR Mask Reset None Reserved ...
Page 86
... QC3CR (Q3FIE) $AA QC3CR (Q3EIE) $A8 QC3CR (Q3VIE) $A6 QC4CR (Q4FIE) $A4 QC4CR (Q4EIE) $A2 QC4CR (Q4VIE) $A0 QC12DCR (DVFIE) $9E QC12DCR (DVEIE) $9C QC12DCR (DVTIE) $9A QC34DCR (DVFIE) $98 QC34DCR (DVEIE) $96 QC34DCR (DVTIE) $94 Reserved $92 Reserved $90 HCFG (IE) $8E CFSCR1 $8C CFSCR1 $8A MSIC (INTE, DTRQIE, $88 DTCMPIE, FAEEN) SDINTREN $86 SMIMR(INTEN) $84 SMIMR(INTEN) $82 Reserved $80 Freescale Semiconductor ...
Page 87
... Refer to the PIM Block Guide for reset configurations of all peripheral module ports. Refer to for location of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table 5-2 Reset Summary ...
Page 88
... HCS12 Module Mapping Control (MMC) Block Description Consult the HCS12 MMC Block Guide for information about the Module Mapping Control module. Section 7 ATA5 Host Controller (ATA5HC) Block Description Consult the ATA5HC Block Guide for information about the ATA5 host controller module. 88 Freescale Semiconductor ...
Page 89
... The CRG_U is part of the IPBus domain. The register space for the CRG_U is located at addresses $0034-$003F. Section 10 Flash EEPROM 32K (FTS32K) Block Description Consult the FTS32K Block Guide for information about the 32K Flash EEPROM module. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 89 ...
Page 90
... The Channel Request Mapping for the IQUE module on the UF32 is shown in Table 11-1. Table 11-1 Queue Channel n Request Mapping QnREQ Peripheral Function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 90 Direction (Rx/Tx) USB20D6E2F Rx USB20D6E2F Tx ATA5HC Rx ATA5HC Tx CFHC Rx CFHC Tx MSHC Rx MSHC Tx SDHC Rx SDHC Tx SMHC Rx SMHC Tx Freescale Semiconductor ...
Page 91
... Only Pierce oscillator/external clock circuitry is allowed. The XCLKS input of the OSC module is tied internally. Figure 13-1 Pierce Oscillator Connections MCU Section 14 Port Integration Module (PIM) Block Description Consult the PIM_9UF32 Block Guide for information about the Port Integration Module. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 EXTAL 12MHz crystal ...
Page 92
... Device-specific information The SDHC is part of the IQUE bus domain. The register spaces for the SDHC is located at addresses $02C0-$02DF. Section 17 Smartmedia Host Controller (SMHC) Block Description Consult the SMHC Block Guide for information about the Smartmedia host controller module. 92 Freescale Semiconductor ...
Page 93
... Section 20 USB2.0 Controller (USB20D6E2F) Block Description Consult the USB20D6E2F Block Guide for information about the USB2.0 Device Controller module. 20.1 Device-specific information The USB 2.0 Serial Interface Engine (USB20SIE) is part of the IQUE bus domain. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 93 ...
Page 94
... MC9S12UF32 design items: • Operation mode • Clocks • Power • USB connector (CON1) • Background debug connector (CON2) To configure the MC9S12UF32 in normal single-chip mode, the MODC, MODB, and MODA pins should be configured as documented in the device overview chapter of this book. 94 Freescale Semiconductor ...
Page 95
... For proper operation of USB and storage interface of the MC9S12UF32, a 12-MHz crystal is required to provide the clock input to the integrated USB PHY. The crystal must connect to the MC9S12UF32 in a Pierce configuration by the XTAL and EXTAL pins as shown. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 1 ...
Page 96
... DPF resistor impedance matching resistors depend on board design DMH resistor DMF resistor RREF resistor See Voltage Regulator Appendix RPU resistor OSC load cap OSC load cap See crystal manufacturer’s recommendations OSC resistor Quartz Value >=100nF >=100nF 100nF 100nF 100nF Freescale Semiconductor ...
Page 97
... VSSA1 and VSSR are connected by anti-parallel diodes for ESD protection. NOTE: IDD3 denotes the currents flowing into VDD3X IDDR denotes the currents flowing into the VDDR IDDX denotes the current flowing into VDDX Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 97 ...
Page 98
... Insure external supply load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e. system clock is present clock rate is very low which would reduce overall power consumption. 98 > supply rail voltage) is greater in Freescale Semiconductor ...
Page 99
... DDA 4. This pin is clamped low to V A.1.6 ESD Protection and Latch-up Immunity During the device qualification, ESD stresses were performed for the Human Body Model (HBM) and the Machine Model (MM). Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Rating Symbol V ...
Page 100
... This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. 100 Description Rating Symbol Symbol Value Unit R1 1500 Ohm C 100 Ohm C 200 -2.5 7.5 Min Max 2000 - HBM V 200 - MM I +100 - LAT -100 Freescale Semiconductor V V Unit ...
Page 101
... Ambient Temperature Total Chip Power Dissipation, [W] = Package Thermal Resistance, [ C/W] JA The total power dissipation can be calculated from: P INT = Chip Internal Power Dissipation, [W] Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table A-4 Operating Conditions Symbol V DDR V DDX V DD3x DDA VSSX ...
Page 102
... Thermal Resistance LQFP64, single layer PCB 3 T natural convection. Thermal Resistance LQFP64, four layer PCB natural 4 T convection. NOTES: 1. The values for thermal resistance are achieved by package simulations 102 P INT = I DDR V DDR DSON i i Symbol Min Typ Max Unit C/W Freescale Semiconductor ...
Page 103
... A.1.9 I/O Characteristics This section describes the characteristics of all 3.3V/5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 103 ...
Page 104
... OL I PUL IL I PUH IH I PDH Min PDL Max PUA I PDA I PDB I PDC ICS I ICP Min Typ Max 0.65 DD5 DD5 0.35 DD5 SS5 250 –2.5 - 2.5 V – 0 DD5 - - 0 –130 - 130 100 120 -2.5 - 2.5 -25 25 Freescale Semiconductor Unit ...
Page 105
... VDDX, VDD3X). DD5 2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each the temperature range from 125 C. 3. Refer to Section A.1.4 Current Injection, for more details Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 105 ...
Page 106
... IL V HYS I in SS3 PUL Max PUH Min PDH I PDL I PUA I PDA I PDB I PDC ICS I ICP Min Typ Max 0.65 DD3 - V + 0.3 - DD3 0.35 DD3 SS3 250 –2.5 - 2.5 V – 0 DD3 - - 0 – 100 120 -2.5 - 2.5 -25 25 Freescale Semiconductor Unit ...
Page 107
... Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each the temperature range from 125 C. 3. Refer to Section A.1.4 Current Injection, for more details Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 107 ...
Page 108
... P Stop Current NOTES: 1. These parameters are achieved by characterization on a small sample size from typical devices. 108 Rating Symbol I DDR I All modules enabled DDW DDS Min Typ Max Unit 1 150 250 230 140 1 100 300 1 300 100 300 1 200 Freescale Semiconductor A ...
Page 109
... The time to program a consecutive word can be calculated as: The time to program a whole row is: Burst programming is more than 2 times faster than single word programming. A.2.1.3 Sector Erase Erasing a 512 byte Flash sector takes: Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01. ...
Page 110
... NVMOP t swpgm t bwpgm t brpgm t era t mass t check cyc Min Typ Max 0 150 200 2 46 74 678.4 1035 26.7 4 100 133 5 11 32778 and maximum bus frequency NVMOP and bus frequency f NVMOP . NVMOP Freescale Semiconductor Unit 1 MHz MHz kHz cyc . bus ...
Page 111
... Num C Data Retention at an average junction temperature Javg 2 C Flash number of Program/Erase cycles NOTES: 1. Data Retention at maximum guaranteed device operating temperature year. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Rating Symbol t NVMRET n FLPE Min Typ Max Unit 15 Years 10,000 ...
Page 112
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 112 Freescale Semiconductor ...
Page 113
... PHY. No external DC load is allowed. Table A-11 Voltage Regulator Recommended Load Resistances/Capacitances Rating Load Capacitance between VDDA and VSSA1 RPU resistor between VDDA and RPU RREF resistor between RREF and VSSA1 Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Symbol Min Typ C ...
Page 114
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 114 Freescale Semiconductor ...
Page 115
... When external reset is asserted for a time greater than PW reset, and the CPU starts fetching the reset vector if there was an oscillation before reset. A.4.1.4 Stop Recovery Out of STOP, the controller can be woken external interrupt. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Table A-12 Startup Characteristics Rating ...
Page 116
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 A.4.1.5 Wait Recovery The oscillator is not stopped in Wait. The controller can be woken up by internal or external interrupts. After t the CPU starts fetching the interrupt vector. wrs 116 Freescale Semiconductor ...
Page 117
... The generated 60MHz clock is assumed correct (locked) if there are exactly 15 clock cycles in 3 oscillator clock cycles. For the electrical characteristics of the USB PHY, please refer to Chapter 7 “Electrical” of Universal Serial Bus Specification Revision 2.0. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 Symbol Min ...
Page 118
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 118 Freescale Semiconductor ...
Page 119
... ECLK PE4 5 9 Addr/Data data (read) PA, PB Addr/Data data (write) PA R/W PE2 20 LSTRB PE3 23 NOACC PE7 26 PIPO0 PIPO1, PE6,5 Figure A-1 General External Bus Timing Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01. addr addr data 14 13 data 19 22 ...
Page 120
... ACCE EH DSR t RWD – RWD RWV t RWH t LSD – LSD LSV t LSH t NOD – NOD NOV t NOH t P0D – P0D P0V P1D EH P1V t P1V where N=0,1 depending on the number of clock stretches. cyc Min Typ Max 0 30 Freescale Semiconductor Unit MHz ...
Page 121
... Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 121 ...
Page 122
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 122 Freescale Semiconductor ...
Page 123
... Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12UF32 packages. Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 123 ...
Page 124
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 B.2 100-pin LQFP Package Figure B-1 100-pin LQFP mechanical dimensions (case no. 983) 124 Freescale Semiconductor ...
Page 125
... H A– VIEW D1/2 D SEATING C PLANE X X= e/2 AB 60X VIEW Y Figure B-2 64-pin LQFP mechanical dimensions (case no. 840F) Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01. TIPS 0.2 C A– E1 VIEW AA BASE METAL b1 c PLATING b e 0.08 C A– ...
Page 126
... System on a Chip Guide — 9S12UF32DGV1/D V01.05 126 Freescale Semiconductor ...
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... System on a Chip Guide End Sheet Freescale Semiconductor System on a Chip Guide — 9S12UF32DGV1/D V01.05 127 ...
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... System on a Chip Guide — 9S12UF32DGV1/D V01.05 128 FINAL PAGE OF 128 PAGES Freescale Semiconductor ...