MC9S12UF32PB Freescale Semiconductor, MC9S12UF32PB Datasheet - Page 66

• Manufacturer Part Number: MC9S12UF32PB
• Description: IC MCU 32K FLASH 30MHZ 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12UF32PB

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: ATA, Compact Flash, EBI/EMI, Memory Stick, MMC, SCI, SD, Smart Media, USB
• Peripherals: POR, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.5K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

System on a Chip Guide — 9S12UF32DGV1/D V01.05
2.4.52 PT[3:0] / IOC[3:0]— Port T I/O Pins [3:0]
PT[3:0] are general purpose input or output pins. When the Timer system (TIM) is enabled they can also
be configured as the TIM input capture or output compare pins IOC[3:0]. While in reset and immediately
out of reset the PT[3:0] pins are configured as a high impedance input pins. Consult the Port Integration
Module (PIM) PIM_9UF32 Block Guide and the TIM_16B8C Block Guide for information about pin
configurations.
2.4.53 PU[5:3] / CFA[2:0] / ATADA[2:0] — Port U I/O Pins [5:3]
PU[5:3] are general purpose input or output pins. When the compact flash host controller (CFHC) is
enabled PU[5:3] becomes the compact flash address pin, CFA[2:0]. When the CFHC is not enabled, it can
be configured as the ATA address pin, ATADA[2:0], when the ATA5 host controller (ATA5HC) is
enabled. While in reset and immediately out of reset the PU[5:3] pin is configured as a high impedance
input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide
and the ATA5HC Block Guide for information about pin configurations.
2.4.54 PU2 / CFREG — Port U I/O Pin 2
PU2 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PU2 becomes the compact flash register select pin, CFREG. While in reset and immediately out of reset
the PU2 pin is configured as a high impedance input pin. Consult the Port Integration Module (PIM)
PIM_9UF32 Block Guide and the CFHC Block Guide for information about pin configurations.
2.4.55 PU1 / CFINPACK / ATADMACK — Port U I/O Pin 1
PU1 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PU1 becomes the compact flash input acknowledge pin, CFINPACK. When the CFHC is not enabled, it
can be configured as the ATA DMA acknowledge pin, ATADMACK, when the ATA5 host controller
(ATA5HC) is enabled. While in reset and immediately out of reset the PU1 pin is configured as a high
impedance input pin. Consult the Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC
Block Guide and the ATA5HC Block Guide for information about pin configurations.
2.4.56 PU0 / CFWAIT / ATAIORDY — Port U I/O Pin 0
PU0 is a general purpose input or output pin. When the compact flash host controller (CFHC) is enabled
PU0 becomes the compact flash wait pin, CFWAIT. When the CFHC is not enabled, it can be configured
as the ATA I/O ready pin, ATAIORDY, when the ATA5 host controller (ATA5HC) is enabled. While in
reset and immediately out of reset the PU0 pin is configured as a high impedance input pin. Consult the
Port Integration Module (PIM) PIM_9UF32 Block Guide, the CFHC Block Guide and the ATA5HC
Block Guide for information about pin configurations.
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