MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 120

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

9.4.2 Timer Interrupt Flag Register 2
TFLG2 — Timer Interrupt Flag 2
TOF — Timer Overflow Interrupt Flag
RTIF — Real-Time Interrupt Flag
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Not implemented
9.4.3 Pulse Accumulator Control Register
PACTL — Pulse Accumulator Control
Bit 7 — Not implemented
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
9-14
RESET:
RESET:
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
Clear flags by writing a one to the corresponding bit position(s).
Set when TCNT changes from $FFFF to $0000
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Always read zero
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits con-
trol the pulse accumulator and IC4/OC5 functions.
Always reads zero
Refer to 9.6 Pulse Accumulator.
Refer to 9.6 Pulse Accumulator.
Bit 7
TOF
Bit 7
—
0
0
PAEN
RTIF
6
0
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
PAMOD
PAOVF
5
0
5
0
Go to: www.freescale.com
TIMING SYSTEM
PEDGE
PAIF
4
0
4
0
—
—
0
0
3
3
I4/O5
—
2
0
2
0
RTR1
—
1
0
1
0
TECHNICAL DATA
RTR0
Bit 0
Bit 0
—
0
0
MC68HC11F1
$1025
$1026