MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 83

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

PORTC — Port C Data
DDRC — Data Direction Register for Port C
DDC[7:0] — Data Direction for Port C
6.4 Port D
PORTD — Port D Data
TECHNICAL DATA
S. Chip or
RESET:
Expan. or
RESET:
RESET:
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port C can only be configured for wired-OR operation when the MCU is in sin-
gle-chip or bootstrap modes.
In all modes, port D bits [5:0] can be used either for general-purpose I/O, or with the
SCI and SPI subsystems. During reset, port D pins are configured as high impedance
inputs (DDRD bits cleared).
The DWOM control bit in the SPCR register disables port D’s P-channel output drivers.
Because the N-channel driver is not affected by DWOM, setting DWOM causes port
D to become an open-drain-type output port suitable for wired-OR operation. In wired-
OR mode, (PORTD bits are at logic level zero), pins are actively driven low by the N-
channel driver. When a port D bit is at logic level one, the associated pin is in a high-
impedance state, as neither the N-channel nor the P-channel devices are active. It is
customary to have an external pull-up resistor on lines that are driven by open-drain
devices. Port D can be configured for wired-OR operation in any operating mode.
Alt. Pin
Func.:
Boot:
Test:
0 = Input
1 = Output
DATA7
DDC7
Bit 7
PC7
PC7
Bit 7
Bit 7
—
—
0
0
I
DATA6
DDC6
PC6
PC6
—
—
6
6
0
6
0
I
Freescale Semiconductor, Inc.
For More Information On This Product,
DATA5
DDC5
PC5
PC5
PD5
SS
5
5
0
5
I
I
PARALLEL INPUT/OUTPUT
Go to: www.freescale.com
DATA4
DDC4
SCK
PC4
PC4
PD4
4
4
0
4
I
I
DATA3
DDC3
MOSI
PC3
PC3
PD3
0
3
3
3
I
I
DATA2
DDC2
MISO
PC2
PC2
PD2
2
2
0
2
I
I
DATA1
DDC1
PC1
PC1
PD1
TxD
1
1
0
1
I
I
DATA0
DDC0
Bit 0
Bit 0
Bit 0
PC0
PC0
PD0
RxD
0
I
I
$1006
$1007
$1008
6-3