MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 50

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

ADPU — A/D Power-Up
CSEL — Clock Select
IRQE — Configure IRQ for Falling Edge-Sensitive Operation
DLY — Enable Oscillator Start-up Delay
CME — Clock Monitor Enable
FCME — Force Clock Monitor Enable
CR[1:0] — COP Timer Rate Select Bits
4.3.2.4 OPT2 Register
4-12
Refer to SECTION 10 ANALOG-TO-DIGITAL CONVERTER.
Selects alternate clock source for on-chip EEPROM and A/D charge pumps. On-chip
RC clock should be used when E clock falls below 1 MHz. Refer to SECTION 10 AN-
ALOG-TO-DIGITAL CONVERTER.
Refer to SECTION 5 RESETS AND INTERRUPTS.
Refer to SECTION 5 RESETS AND INTERRUPTS.
In order to use both STOP and clock monitor, the CME bit must be written to zero be-
fore executing STOP, then written to one after recovering from STOP. Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
When FCME equals one, slow or stopped clocks will cause a clock failure reset. To
use STOP mode, FCME must always equal zero. Refer to SECTION 5 RESETS AND
INTERRUPTS.
These control bits determine a scaling factor for the watchdog timer. Refer to SEC-
TION 5 RESETS AND INTERRUPTS.
The system configuration options 2 register (OPT2) controls three additional system
options.
0 = A/D system disabled
1 = A/D system power enabled
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
0 = Low level-sensitive operation.
1 = Falling edge-sensitive only operation.
0 = The oscillator start-up delay coming out of STOP is bypassed and the MCU re-
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
0 = Clock monitor disabled
1 = Clock monitor enabled
0 = Clock monitor follows state of CME bit
1 = Clock monitor enabled and cannot be disabled until next reset
sumes processing within about four bus cycles.
up from the STOP power-saving mode.
Freescale Semiconductor, Inc.
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
Go to: www.freescale.com
TECHNICAL DATA
MC68HC11F1