R5F21238JFP#U0 Renesas Electronics America, R5F21238JFP#U0 Datasheet - Page 129

• Manufacturer Part Number: R5F21238JFP#U0
• Description: IC R8C/23 MCU FLASH 64K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 12.8
Figure 12.9
Address
12.1.6.7
m−4
m−3
m−2
m−1
m+1
m
Stack state before interrupt request
is acknowledged
In the interrupt sequence, the FLG register and PC are saved to the stack.
After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, extended to
16 bits, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used
NOTE:
The register saving operation which is performed in the interrupt sequence is saved in 8 bits every 4 steps.
Figure 12.9 shows the Register Saving Operation.
MSB
Content of previous stack
Content of previous stack
1. Selectable from the R0, R1, R2, R3, A0, A1, SB and FB registers.
Address
NOTE:
[SP]−5
[SP]−4
[SP]−3
[SP]−2
[SP]−1
Saving a Register
Stack
Stack State Before and After Acknowledgement of Interrupt Request
Register Saving Operation
[SP]
1. [SP] indicates the initial value of the SP when interrupt request is acknowledged.
NOTE:
After registers are saved, the SP content is [SP] minus 4.
software number 32 to 63 INT instructions, this SP is specified by the
U flag. Otherwise it is ISP.
1. When executing the software number 32 to 63 INT instructions, this
SP is specified by the U flag. Otherwise it is ISP.
FLGH
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LSB
Stack
PCM
FLGL
PCL
[SP]
SP value before
interrupt is generated
PCH
Sequence in which
order registers are
saved
Completed saving
registers in four
operations.
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
Address
m−4
m−3
m−2
m−1
m
m+1
When executing the
Stack state after interrupt request
is acknowledged
MSB
Content of previous stack
Content of previous stack
FLGH
PCH
PCM
PCL
FLGH
FLGL
FLGL
PCM
PCL
Stack
: High-order 4 bits of PC
: Low-order 8 bits of PC
: Middle-order 8 bits of PC
: High-order 4 bits of FLG
: Low-order 8 bits of FLG
PCH
(1)
LSB
with 1 instruction.
PCH
PCM
PCL
FLGH
FLGL
[SP]
New SP value
: High-order 4 bits of PC
: Middle-order 8 bits of PC
: Low-order 8 bits of PC
: High-order 4 bits of FLG
: Low-order 8 bits of FLG
12. Interrupts