R5F21238JFP#U0 Renesas Electronics America, R5F21238JFP#U0 Datasheet - Page 33

• Manufacturer Part Number: R5F21238JFP#U0
• Description: IC R8C/23 MCU FLASH 64K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3.
R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The
same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register
(R2R0). The same applies R3R1 as R2R0.
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also
are used for transfer, arithmetic and logic operations. The same applies to A1 as A0.
A1 can be combined with A0 to be used a 32-bit address register (A1A0).
FB is a 16-bit register for FB relative addressing.
INTB, a 20-bit register, indicates the start address of an interrupt vector table.
PC, 20 bits wide, indicates the address of an instruction to be executed.
The stack pointer (SP), USP and ISP, are 16 bits wide each.
The U flag of FLG is used to switch between USP and ISP.
SB is a 16-bit register for SB relative addressing.
FLG is a 11-bit register indicating the CPU status.
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
The D flag is for debug only. Set to 0.
The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.
The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.
The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.
The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.
Data Registers (R0, R1, R2 and R3)
Address Registers (A0 and A1)
Frame Base Register (FB)
Interrupt Table Register (INTB)
Program Counter (PC)
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Static Base Register (SB)
Flag Register (FLG)
Carry Flag (C)
Debug Flag (D)
Zero Flag (Z)
Sign Flag (S)
Register Bank Select Flag (B)
Overflow Flag (O)
Page 11 of 501
2. Central Processing Unit (CPU)