R5F21238JFP#U0 Renesas Electronics America, R5F21238JFP#U0 Datasheet - Page 371

• Manufacturer Part Number: R5F21238JFP#U0
• Description: IC R8C/23 MCU FLASH 64K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.45
16.3.6
Table 16.8
1 Tcyc = 1/f1(s)
When setting the I
Figure 16.45 shows the Timing of Bit Synchronous Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
•
•
When the SCL signal is driven to “L” by the slave device.
Since the “H” period may become shorter while the SCL signal is driven to “L” by the slave device and the
rising speed of the SCL signal is lowered by the load (load capacity and pull-up resistor) of the SCL line,
the SCL signal is monitored and the communication synchronizes per bit.
Bit Synchronization Circuit
CKS3
0
1
Monitoring of SCL Signal
Timing of Bit Synchronous Circuit
Time between Changing SCL Signal from “L” Output to High-Impedance and
ICCR1 Register
Basis clock of SCL
2
C bus interface in master mode.
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monitor timing
Internal SCL
SCL
CKS2
0
1
0
1
VIH
Time for Monitoring SCL
16. Clock Synchronous Serial Interface
19.5 Tcyc
17.5 Tcyc
41.5 Tcyc
7.5 Tcyc