R5F21238JFP#U0 Renesas Electronics America, R5F21238JFP#U0 Datasheet - Page 334

• Manufacturer Part Number: R5F21238JFP#U0
• Description: IC R8C/23 MCU FLASH 64K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238JFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
16.2.5.4
Data transmit/receive is a combined operation of data transmit and receive which are described before.
Transmit/receive is started by writing data in the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error occurs) while the TDRE bit is set to 1 (data
is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =1),
set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the TDRE
bit is set to 0 when the last bit of the transmit data is transmitted), the RERF bit is set to 0 (no data in the
SSRDR register) and the ORER bit is set to 0 (no overrun error), set the TE and RE bits to 1.
Figure 16.17 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if transmit/
receive mode is exited after reading the SSRDR register. To avoid any clock outputs, perform either of the
following:
•
•
When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit
to 0 to reset the clock synchronous serial interface control unit and the SSTRSR register. Then, set the RE bit to
1.
First set the RE bit to 0, and then set the TE bit to 0.
Set bits TE and RE at the same time.
Data Transmission/Reception
Page 312 of 501
16. Clock Synchronous Serial Interface