ISL88001IH31Z-TK Intersil, ISL88001IH31Z-TK Datasheet - Page 6

• Manufacturer Part Number: ISL88001IH31Z-TK
• Description: IC VOLT SUPERVISOR 3.09V SOT23-3
• Manufacturer: Intersil
• Type: Simple Reset/Power-On Resetr

Specifications of ISL88001IH31Z-TK

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 3.075V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-3, TO-236-3, Micro3™, SSD3, SST3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Specifications
NOTE:
Pin Description
RST
The ISL88003 push-pull RST output is set to V
whenever the device is first powered up or V
its respective minimum voltage sense level.
RST
The RST output functions identically to the complementary
RST output. On the ISL88001, this is a push-pull output. On
the ISL88002, it is an open drain output that is pulled to GND
(LOW) when reset is asserted. Suggested pull-up RST
resistor values are in the range of 5kΩ to 100kΩ.
V
The V
pin is compared against an internal factory-programmed
voltage trip point, V
device is initially powered up to ensure that the power supply
has stabilized. Thereafter, reset is again asserted whenever
V
hysteresis to help prevent chattering due to noise.
Principles of Operation
The ISL88001, ISL88002, ISL88003 devices provide a low
power, high accuracy solution for those voltage monitoring
applications needing supply voltage supervision with power
reset control. By integrating these features into small 3 Ld
SC-70 and 3 Ld SOT-23 packages and consuming as little
as 160nA of supply current, these devices can lower system
cost and reduce board space requirements.
Low Voltage Monitoring
During normal operation, the ISL88001, ISL88002,
ISL88003 devices monitor the voltage level of V
device asserts a reset signal (RST = LOW or RST = HIGH)
RESET / RESET
V
V
t
t
C
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
RPD
POR
DD
DD
OL
OH
LOAD
SYMBOL
falls below V
DD
pin is the power supply terminal. The voltage at this
Reset Output Voltage Low
Reset Output Voltage High
V
POR Timeout Delay
Load Capacitance on Reset Pin
TH
THVDD
THVDD
to Reset Asserted Delay
. The device is designed with
. A reset is first asserted when the
PARAMETER
6
Over the recommended operating conditions unless otherwise specified. (Continued)
ISL88001, ISL88002, ISL88003
DD
DD
DD
falls below
(HIGH)
. The
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
< V
< V
> V
> V
> V
< V
THVDD,
THVDD,
THVDD
THVDD
THVDD
THVDD
TEST CONDITIONS
, for ISL88003
, for ISL88001
, Sourcing 0.5mA, ISL88002
, for ISL88003
for ISL88001
Sinking 0.5mA for ISL88002
to a µP/µC if this voltage is less than the preset voltage trip
point. The reset signal prevents system operation during a
power failure or brownout condition. This reset signal
remains asserted until V
setting for the reset time delay period t
Power-On Reset (POR)
Applying power to the ISL88001, ISL88002, ISL88003
activates a POR circuit, which asserts reset once V
(i.e. RST goes LOW). This provides several benefits:
• It prevents the system microprocessor from starting to
• It prevents the processor from operating prior to
• It ensures that the monitored device is held out of
• It allows time for an FPGA to download its configuration
operate with insufficient voltage.
stabilization of the oscillator.
operation until internal registers are properly loaded.
prior to initialization of the circuit.
V
DD
FIGURE 1. TYPICAL APPLICATION DIAGRAM
GND
V
ISL88002*
ISL88001
ISL88003
DD
*Necessary for ISL88002
OUTPUT
RESET
V
V
DD
(Note 4)
DD
DD
MIN
140
exceeds the voltage threshold
- 0.4 V
- 0.4 V
R
PU
V
*
DD
DD
DD
RESET
INPUT
TYP
200
0.2
0.2
0.2
15
5
POR
- 0.2
- 0.2
- 0.2
GND
. See Figure 2.
V
(Note 4) UNITS
DD
µP/µC
MAX
0.40
0.40
0.40
260
March 26, 2008
DD
FN6174.0
= 1 V.
ms
pF
µs
V
V
V
V
V
V