MCF5274LVM166 Freescale Semiconductor, MCF5274LVM166 Datasheet

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... MCF5272 ColdFire microprocessor (10/100 Mbps Ethernet MAC and USB device) by adding a second 10/100 Mbps Ethernet MAC (MCF5274 and MCF5275) and hardware encryption (MCF5275L and MCF5275). © Freescale Semiconductor, Inc., 2009. All rights reserved. ® family of reduced 1 MCF5275 Family Configurations . . . . . . . . . . . . . . . . . . . 2 2 Block Diagram ...

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... MAPBGA 256 MAPBGA Freescale Semiconductor • 2 • • • • 2 • • 4 • • 3 • 4 • • • • • ...

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... Cryptography Modules (To/From PADI) 3 Features For a detailed feature list see the MCF5275 Reference Manual (MCF5275RM). MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor shows a top-level block diagram of the MCF5275, the superset device. (To/From SRAM backdoor) INTC0 INTC1 Arbiter UART UART ...

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... A11, B11, C11 A8, B8, C8 A12, B12, C12, B9, D9, C9, A13, B13, C13, C10, B10, A11, A14, B14, C14, C11, B11, A12, B15, C15, B16, D11, C12, B13, C16, D14, D15, C13, D12, E11, E14:16, F14:16 D13, E12, F11, D14, E13, F13 Freescale Semiconductor ...

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... SD_A10 — SD_DQS[3:2] PSDRAM[2:1] SD_CKE PSDRAM[0] SD_VREF — IRQ[7:5] PIRQ[7:5] IRQ[4] PIRQ[4] IRQ[3:2] PIRQ[3:2] MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor MCF5274 1 Alternate1 Alternate2 Dir. MCF5275 256 MAPBGA — — O M1, N1, N2, N3, P1, P2, R1, R2, P3, R3, T3, N4, P4, R4, T4, N5 CAS[3:2] — ...

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... I — — I — — I — — O E1, E2, F2 — — O — — I B1, B2, A2 — — I MCF5274L MCF5275L 196 MAPBGA K13 J13 D1, E3 D4, B1 — G2 — C1 — D2 — F1 — A5 — B4 — A3 — B3 — A4 — — D1 — — C2 — Freescale Semiconductor ...

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... PUARTL[6] U1CTS PUARTL[5] U1RTS PUARTL[4] U0RXD PUARTL[3] U0TXD PUARTL[2] U0CTS PUARTL[1] U0RTS PUARTL[0] USB_SPEED PUSBH[0] USB_CLK PUSBL[7] MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor MCF5274 1 Alternate1 Alternate2 Dir. MCF5275 256 MAPBGA U2RXD — I/O U2TXD — I/O DMA QSPI ...

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... MAPBGA J16 H13 J15 J11 L15 L14 M13 N13 K14 J14 K15 J12 L14 K13 P14 P13 P16 P12 R15 N12 R16 M12 P15 K11 R14 P11 M7, N7, P8, L9 N11 P7, L8, M8, N8 R11 N9 N6 M14 — M15 M13 Freescale Semiconductor ...

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... Use 6 mils trace and separation. Clocks get extra separation and more precise balancing. 5.2 Power Supply 33uF, 0.1 μF, and 0.01 μF across each power supply • MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor MCF5274 1 Alternate1 Alternate2 Dir. MCF5275 256 MAPBGA — ...

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... There is no limit on how DD DD must powered up /SDV should track up to 0.9 V, then separate for the completion of DD going to the higher external voltages. One way to accomplish this (SDV ), PLL SDV , PLLV SDV (2.5V Time . should not lead the OV DD Freescale Semiconductor ...

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... Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. • Tie XTAL to ground when an external oscillator is clocking the device. MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor powers down before SDV , or PLLV ...

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... Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Transmit clock Transmit enable Transmit data Transmit error MCF5275 Integrated Microprocessor Family Hardware Specification, Rev Description Table 4. MII Mode Signal Description MCF5275 Pin FECn_TXCLK FECn_TXEN FECn_TXD[3:0] FECn_TXER Table 4. Freescale Semiconductor ...

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... Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for this board are accessible at the MCF5275 site by navigating to: http://www.freescale.com/coldfire. MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 4. MII Mode (continued) Signal Description FECn_COL ...

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... RSTOUT RESET CS2 MOD1 QSPI_ CLK TRST/ CS0 MOD0 DSCLK QSPI_ QSPI_ JTAG_ PST2 PST0 DOUT CS3 EN QSPI_ QSPI_ PST3 PST1 CLKOUT DIN CS1 Freescale Semiconductor 15 16 SD_ VSS A VREF A11 A9 B A10 TSIZ1 USB_ TSIZ0 G CLK IRQ5 IRQ6 H USB_RP USB_RN J ...

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... MCF5275 256 MAPBGA package dimensions LASER MARK FOR PIN A1 Y IDENTIFICATION IN THIS AREA E 0.20 15X 15X VIEW M-M Figure 4. 256 MAPBGA Package Dimensions MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA 256X ...

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... OVDD TDO/DSO RESET QSPI_ DDATA0 QSPI_CLK RSTOUT DOUT QSPI_ QSPI_DIN CLKMOD1 TDI/DSI CS0 QSPI_ QSPI_ CLKMOD0 TMS/BKPT CS2 CS1 QSPI_ TCLK/PST CLKOUT JTAG_EN CS3 CLK Freescale Semiconductor 13 14 SD_ NC A VREF A9 TSIZ1 B A8 CS2 TSIZ0 E A0 IRQ7 F IRQ6 IRQ5 G USB_RN IRQ3 ...

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... MCF5275 196 MAPBGA package dimensions Laser mark for pin 1 Y identification in this area E TOL 13X e 3 196X b View M-M 0. 0.08 Z Figure 6. 196 MAPBGA Package Dimensions MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor 13X e S Metalized mark for pin 1 identification this area ...

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... Ordering Information 7 Ordering Information Freescale Part Number MCF5274LVM166 MCF5274L RISC Microprocessor MCF5274LCVM166 MCF5274VM166 MCF5274 RISC Microprocessor MCF5274CVM166 MCF5275LCVM166 MCF5275L RISC Microprocessor MCF5275CVM166 MCF5275 RISC Microprocessor 8 Electrical Characteristics This appendix contains electrical specification tables and reference timing diagrams for the MCF5275 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5275 ...

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... A Θ = Package Thermal Resistance, Junction-to-Ambient, °C/W JMA + INT MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor and and could result in external power supply going out of DD load shunts current greater than maximum injection current. This DD range during instantaneous and operating maximum current conditions. ...

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... P 2 (3) A JMA D and Table 9. ESD Protection Characteristics Symbol and T ( can be obtained by solving equations ( Value Units HBM 2000 V MM 200 V Ω R 1500 series C 100 pF Ω series C 200 pF — — 1 — 1 — — 3 — 3 — 1 sec Freescale Semiconductor is I/O (at D ...

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... High Impedance (Off-State) Leakage Current All input/output and output pins Weak Internal Pull Up Device Current, tested Input Capacitance All input-only pins All input/output (three-state) pins MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 10. DC Electrical Specifications Symbol V = 2.5V 3.3V Max. IL ...

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... DD > greater than I , the injection current may flow out Min Max Unit pF — 25 — 50 — 175 mA — — μA — 100 — 250 mA μA — 250 mA -1.0 1.0 - and could DD load shunts current greater than Freescale Semiconductor ...

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... All values given are initial design targets and subject to change. 2 All internal registers retain data at 0 Hz. 3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode. MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 11. PLL Electrical Specifications Symbol f ref_crystal f ref_ext ...

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... DD DDPLL , and τ = 1.57x10 -6 x 2(MFD + 2) ref_1:1 maximum specified value. Modulation sys/2 Symbol Min Max Unit t 12 — CYC t 9 — CVCH t 9 — BKVCH t 0 — CHCII t 0 — BKNCH t 4 — DIVCH t 0 — CHDII Freescale Semiconductor ...

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... B7a CLKOUT high to chip selects invalid B8 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Figure 7. T SETUP T HOLD Invalid Valid ...

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... Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing MCF5275 Integrated Microprocessor Family Hardware Specification, Rev Symbol Data Outputs t CHDOV t CHDOI t CHDOZ Table 13 are shown in Figure B7a B6a B6b B7 B11 B4 B5 Min Max — 9 1.0 — — 9 Figure 9, and Figure 10 B7a B12 B13 Freescale Semiconductor Unit ...

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... TA showing timings listed in CLKOUT CSn B8 A[23:0] TSIZ[1: TIP OE (H) R/W BS[3:2] D[31:16] TA TEA (H) Figure 9. SRAM Read Bus Cycle Terminated by TA MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor B6a B7a B9 B6c B6b B5 B4 B1a Electrical Characteristics Table 13 ...

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... SRAM bus cycle terminated by TEA showing timings listed in CLKOUT CSn B8 A[23:0] TSIZ[1: TIP OE (H) R/W BS[3:2] D[31:16] TA (H) TEA Figure 10. SRAM Read Bus Cycle Terminated by TEA MCF5275 Integrated Microprocessor Family Hardware Specification, Rev B6a B7a B9 B6c B6b B1a B2a Table 13 Freescale Semiconductor ...

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... DD10 SD_DQS high to Data invalid (read) - hold DD11 SD_DQS falling edge to CLKOUT high - setup DD12 SD_DQS falling edge to CLKOUT high - hold MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 14. DDR Clock Timing Specifications Characteristic Figure 11. DDR Clock Timing Diagram Table 15 ...

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... DDR SDRAM write cycle. DDR_CLKOUT DDR_CLKOUT Figure 12. DDR_CLKOUT and DDR_CLKOUT Crossover Timing MCF5275 Integrated Microprocessor Family Hardware Specification, Rev Table 15. DDR Timing (continued) 1 Symbol ) t RPRE RPRE ) t RPST RPST ) t WPRE WPRE ) t WPST WPST . CK Min Max Unit 0.9 1 0.4 0 0.25 — 0.4 0 Freescale Semiconductor ...

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... DDR_CLKOUT DDR_CLKOUT SD_CSn,SD_WE, SD_SRAS,SD_SCAS DD4 A[13:0] DM[3:2] SD_DQS[3:2] D[31:16] MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 13. DDR Write Timing Electrical Characteristics DD3 DD7 DD8 DD7 DD8 31 ...

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... Figure 14. DDR Read Timing Table 16. GPIO Timing DD3 DD9 DQS Read Postamble DD10 WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble WD1 WD2 WD3 WD4 Symbol Min Max t — 10 CHPOV t 1.0 — CHPOI t 9 — PVCH t 1.5 — CHPI Freescale Semiconductor Unit ...

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... Thus, RESET must be held a minimum of 100 ns. CLKOUT RESET RSTOUT 1 Configuration Overrides : (RCON, Override pins]) 1. Refer to the Coldfire Integration Module (CIM) section for more information. RESET and Configuration Override Timing MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Figure 15. GPIO Timing (V = 2 ...

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... The transmitter functions correctly FECn_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FECn_TXCLK frequency. MCF5275 Integrated Microprocessor Family Hardware Specification, Rev Table 18. MII Receive Signal Timing Characteristic Table 18 Min Max Unit 5 — — ns 35% 65% FECn_RXCLK period 35% 65% FECn_RXCLK period M4 Freescale Semiconductor ...

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... MII asynchronous inputs signal timing. Table 20. MII Asynchronous Input Signal Timing Num M9 FECn_CRS, FECn_COL minimum pulse width Figure 18 shows MII asynchronous input timings listed in FECn_CRS FECn_COL MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 19. MII Transmit Channel Timing Characteristic Table 19 Characteristic Table M9 Figure 18 ...

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... FECn_MDIO (output) FECn_MDIO (input) Figure 19. MII Serial Management Channel Timing Diagram MCF5275 Integrated Microprocessor Family Hardware Specification, Rev Characteristic M14 M15 M10 M11 M13 M12 Min Max Unit 0 — ns — — — ns 40% 60% MDC period 40% 60% MDC period Table 21. Freescale Semiconductor ...

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... USB_CLK high to USB_TP, USB_TN, USB_SUSP valid US8 USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid Figure 20 shows USB interface timings listed in USB_CLK USB Outputs USB Inputs Input Rise Time Input Fall Time MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 22. USB Interface Timing Characteristic = ...

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... CYC — — ns — — ns CYC 0 — — ns CYC — ns CYC Figure 21. Min Max Units — ns CYC — ns CYC — — µ — ns CYC — — ns CYC — ns CYC — ns CYC — ns CYC Table 24. The are minimum values. Freescale Semiconductor ...

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... Name QS1 QSPI_CS[3:0] to QSPI_CLK QS2 QSPI_CLK high to QSPI_DOUT valid. QS3 QSPI_CLK high to QSPI_DOUT invalid (Output hold) QS4 QSPI_DIN to QSPI_CLK (Input setup) QS5 QSPI_DIN to QSPI_CLK (Input hold) MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Table 23 and Table 24 Figure 21 Input/Output Timings 1 ...

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... QS4 QS5 Symbol Min Max f DC 1/4 JCYC — JCYC CYC t 26 — JCW JCRF t 4 — BSDST t 26 — BSDHT BSDV BSDZ t 4 — TAPBST t 10 — TAPBHT TDODV TDODZ t 100 — TRSTAT t 10 — TRSTST Freescale Semiconductor Unit f sys ...

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... TCLK V Data Inputs Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Freescale Semiconductor Figure 23. Test Clock Input Timing Figure 24. Boundary Scan (JTAG) Timing J9 Input Data Valid J11 ...

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... D1 D2 Figure 27. Real-Time Trace AC Timing Table D5 Current D4 Past Figure 28. BDM Serial Port AC Timing Figure 28. 166 MHz Units Min Max — 0.5 t CYC 4 — ns 1.0 — — ns CYC — ns CYC — ns CYC 4 — ns 1.5 — ns 0.0 10.0 ns 28. Next Current Freescale Semiconductor ...

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... Documentation Documentation regarding the MCF5275 and their development support tools is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale web address at http://www.freescale.com/coldfire. 10 Revision History Table 29 provides a revision history for this hardware specification. ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...