MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 104

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Local Memory
4.2
Table 4-1
4.3
The SRAM module has the following features:
4.3.1
The SRAM module provides a general-purpose memory block the ColdFire core can access in a single
cycle. The location of the memory block can be set to any 4-Kbyte address boundary within the 4-Gbyte
address space. The memory is ideal for storing critical code or data structures or for use as the system stack.
Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly
service core-initiated accesses or memory-referencing commands from the debug module.
Section 4.1, “Interactions Between Local Memory
hits multiple local memory resources.
4.3.2
The MCF5272 implements the SRAM base address register (RAMBAR), shown in
described in the following section.
4-2
•
•
•
•
•
•
•
Addresses not assigned to the register and undefined register bits are reserved. Write accesses to
these bits have no effect; read accesses return zeros.
The reset value column indicates the register initial value at reset. Uninitialized fields may contain
random values after reset.
4-Kbyte SRAM, organized as 1K x 32 bits
Single-cycle access
Physically located on the ColdFire core's high-speed local bus
Byte, word, longword address capabilities
Programmable memory mapping
(using MOVEC)
Local Memory Registers
SRAM Overview
lists the local memory registers. Note the following:
SRAM Operation
SRAM Programming Model
Address
0xC04
0x002
0x004
0x005
0xC00
MCF5272 ColdFire
ROMBAR
RAMBAR
Table 4-1. Memory Map of Instruction Cache Registers
CACR
Name
ACR0
ACR1
Width
32
32
32
32
32
®
Integrated Microprocessor User’s Manual, Rev. 3
Cache control register
Access control register 0
Access control register 1
ROM base address register
SRAM base address register
Modules,” describes priorities when an access address
Description
Uninitialized (except V = 0)
Uninitialized (except V = 0)
Reset Value
0x0000
0x0000
0x0000
Figure 4-1
Freescale Semiconductor
and