MCF5272VM66 Freescale Semiconductor, MCF5272VM66 Datasheet - Page 213

• Manufacturer Part Number: MCF5272VM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272VM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Chapter 10
DMA Controller
The MCF5272 has a one-channel DMA controller that supports memory-to-memory DMA transfers that
can be used for block data moves. This chapter describes in detail its signals, registers, and operating
modes.
10.1
A source and destination address must be specified for any dual-address DMA transfer. These addresses
can have different data transfer types, but there is always a read from the source address followed by a
write to the destination address. On the MCF5272, sources and destinations can be SDRAM, external
SRAM, or on-chip peripheral in any combination.
Note that transfers to on-chip peripherals are limited by the transfer type supported by a specific peripheral.
Freescale Semiconductor
DMA Data Transfer Types
Memory-to-memory DMA transfers run to completion if the assume request
bit in the system configuration register, SCR[AR], is set. This generally
prevents the CPU from recognizing interrupts and blocks bus accesses by
other on-chip bus masters. It is best not to enable SCR[AR] when the DMA
controller is in use. When AR = 0, the DMA controller allows the CPU and
Ethernet controller to obtain bus access.
MCF5272 ColdFire
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Burst (4 x longword)
Transfer Type
Table 10-1. DMA Data Transfer Matrix
®
Integrated Microprocessor User’s Manual, Rev. 3
SDRAM External SRAM On-Chip Peripheral
Yes
Yes
Yes
Yes
Source or Destination Address
NOTE
Yes
Yes
Yes
No
Yes
Yes
Yes
No
10-1