MAC7131MVF40 Freescale Semiconductor, MAC7131MVF40 Datasheet - Page 29

• Manufacturer Part Number: MAC7131MVF40
• Description: IC MCU 32BIT FLASH 208-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MAC7xxxr

Specifications of MAC7131MVF40

• Core Processor: ARM7
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: DMA, POR
• Number Of I /o: 128
• Program Memory Size: 544KB (544K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 32x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 208-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.11 Serial Peripheral Interface
3.11.1 Master Mode
Master mode timing values are shown in
3.11.2 Slave Mode
Slave mode timing values are shown in
Freescale Semiconductor
NOTES:
1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.
2. On mask set L49P and L47W devices,
NOTES:
1. On mask set L49P and L47W devices,
Conditions are shown in
Conditions are shown in
Num C
Num C
U1a P Operating Frequency (baud rate)
U1b P SCK Period (t
U10 D Data Hold Time (Outputs)
U11 D Rise Time Inputs and Outputs
U12 D Fall Time Inputs and Outputs
V1a P Operating Frequency
V1b P SCK Period (t
V10 D Data Hold Time (Outputs)
V11 D Rise Time Inputs and Outputs
V12 D Fall Time Inputs and Outputs
U2
U3
U4
U5
U6
U9
V2
V3
V4
V5
V6
V7
V8
V9
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Slave SIN Disable Time
D Data Valid (after SCK Edge)
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid (after Enable Edge)
D Slave Access Time
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
SCK
SCK
Table 7
Table 7
= 1 ÷ f
= 1 ÷ f
Table 32. SPI Master Mode Timing Characteristics
Table 33. SPI Slave Mode Timing Characteristics
Rating
Rating
unless otherwise noted, C
unless otherwise noted, C
OP
OP
, t
, t
IPS
IPS
U1a
V1a
= 1 ÷ f
= 1 ÷ f
Table 33
Table 32
maximum = ¼ and
maximum = ¼ and
IPS
IPS
)
)
Preliminary
and illustrated in
and illustrated in
LOAD
LOAD
Symbol
Symbol
t
f
SCK
t
t
t
t
t
OP
wsck
wsck
t
f
SCK
t
= 200 pF on all outputs
lead
= 200 pF on all outputs
lead
t
t
t
t
t
lag
t
OP
lag
t
t
t
dis
t
su
ho
t
su
ho
t
t
t
hi
hi
v
a
v
V1b
r
U1b
r
f
f
1
1
minimum = 4.
minimum = 4.
---------------------------- -
7
---------------------------- -
7
t
t
×
IPS
×
IPS
Figure 13
Min
32 678
Min
32 678
2
2
25
25
25
—
—
—
—
—
—
—
—
½
½
0
0
1
1
0
Figure 11
1
1
− 30
− 30
2
1
,
,
and
Typ
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
and
Figure
Figure
Electrical Characteristics
7 × 32,768
7 × 32,768
1024 t
Max
Max
½
½
25
25
25
25
25
25
—
—
—
—
—
14.
—
—
—
—
—
—
1
1
12.
2
1
IPS
Unit
t
t
Unit
f
t
f
t
t
t
t
t
SCK
SCK
IPS
IPS
ns
ns
ns
ns
ns
ns
ns
IPS
IPS
IPS
IPS
ns
ns
ns
IPS
IPS
ns
ns
ns
ns
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