STM32L152-EVAL STMicroelectronics, STM32L152-EVAL Datasheet - Page 10

BOARD EVALUATION FOR STM32L

STM32L152-EVAL

Manufacturer Part Number
STM32L152-EVAL
Description
BOARD EVALUATION FOR STM32L
Manufacturer
STMicroelectronics
Type
MCUr
Datasheets

Specifications of STM32L152-EVAL

New! Us2012 Catalog Page
STM8L-Discovery_STM32L152-EVAL
Contents
Board
Processor To Be Evaluated
STM32L1xxx
Interface Type
UART
Operating Supply Voltage
2 V to 3.6 V
For Use With/related Products
STM32L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10842
Hardware and layout
2.5
2.6
10/44
Boot option
The STM32L152-EVAL evaluation board is able to boot from:
The boot option is configured by setting switch SW1 (BOOT0) and SW2 (BOOT1). The
BOOT0 can also be configured via RS-232 connector CN2.
Table 4.
Table 5.
LCD glass module
An LCD glass module, U20, with 8-digit liquid crystal display is mounted on the
STM32L152-EVAL evaluation board. It is connected to the LCD controller of
STM32L152VBT6.
Table 6.
SW1 and SW2
JP6
JP7
JP8
Jumper
Switch
Jumper
Embedded user Flash
System memory with boot loader for ISP
Embedded SRAM for debugging
PC10 is connected to LCD glass as SEG40 when JP7 is set as shown
(default setting).
PC10 is connected to USART3_TX when JP7 is set as shown.
PC11 is connected to LCD glass as SEG41 when JP8 is set as shown
(default setting).
PC11 is connected to USART3_RX when JP8 is set as shown.
Boot related switches
Boot0 related jumper JP6
LCD glass related jumpers
STM32L152-EVAL boot from embedded user Flash when SW1
is set as shown. SW2 is not relevant in this configuration (default
setting).
STM32L152-EVAL boot from embedded SRAM when SW1 and
SW2 are set as shown.
STM32L152-EVAL boot from system memory when SW1 and
SW2 are set as shown.
Bootloader_BOOT0 is managed by pin 6 of CN2 (RS-232 DSR signal) when JP6
is closed. This configuration is used for boot loader application only.
Default setting: Not fitted.
Doc ID 18141 Rev 1
Description
Boot from
Description
0
0
0
Setting
Setting
UM1018
1
1
1
1
1
1
1
SW1
SW1
SW2
SW1
SW2
2
2
2
2
3
3
3
3

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