IC PROC FM/AM IF SAMPLING 64LQFP

TDA7580

Manufacturer Part NumberTDA7580
DescriptionIC PROC FM/AM IF SAMPLING 64LQFP
ManufacturerSTMicroelectronics
TDA7580 datasheet
 


Specifications of TDA7580

FunctionFM/AM ProcessorFrequency10.7MHz Center
Rf TypeAM, FMSecondary AttributesOn-Chip A/D Converter
Package / Case64-LQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
FM/AM IF sampling DSP
ON-CHIP analogue to digital converter for
10.7MHz IF signal conversion
FM channel equalization
FM adjacent channel suppression
Reception enhancement in multipath condition
Stereo decoder and weak signal processing
2 Channel serial audio interface (SAI) with
sample rate converter
2
I
C and buffer SPI control interfaces
RDS filter, demodulator & decoder
Inter processor transport interface for antenna
and tuner diversity
Front-end AGC feedback
Description
The TDA7580 is an integrated circuit
implementing an advanced mixed analogue and
digital solution, to perform the signal processing
Table 1.
Device summary
Part number
TDA7580
TDA758013TR
March 2007
FM/AM digital IF sampling processor
LQFP64
of an AM/FM channel. The HW & SW architecture
has been devised to perform a digital equalization
of the FM/AM channel, and a real rejection of
adjacent channels and any other signals,
interfering with the listening of the desired station.
In severe multiple path conditions, the reception is
improved to get high quality audio.
Package
LQFP64
LQFP64
Rev 5
TDA7580
Packing
Tube
Tape and reel
1/39
www.st.com
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TDA7580 Summary of contents

  • Page 1

    ... RDS filter, demodulator & decoder ■ Inter processor transport interface for antenna and tuner diversity ■ Front-end AGC feedback Description The TDA7580 is an integrated circuit implementing an advanced mixed analogue and digital solution, to perform the signal processing Table 1. Device summary Part number TDA7580 ...

  • Page 2

    ... High speed serial synchronous interface (HS 8.9 Tuner AGC keying DAC (KEYDAC 8.10 Asynchronous sample rate converter (ASRC band pass Σ Δ analogue to digital converter (IFADC 8.11 8.12 Digital down converter (DDC 8.13 RDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.14 AM/FM Detector (CORDIC Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/39 TDA7580 ...

  • Page 3

    ... TDA7580 9.1 Electrical application scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Contents 3/39 ...

  • Page 4

    ... FM stereo decoder characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 15. Sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 Table 16. SPI and I C timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 17. SAI Timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 18. RDS SPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 19. BSPI timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Table 20 timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 Table 21 BUS timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4/39 TDA7580 ...

  • Page 5

    ... TDA7580 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. PIN connection (top view Figure 3. Power on and boot sequence using I Figure 4. Power on and boot sequence using SPI Figure 5. SAI Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR= Figure 7. SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR= Figure 8. SAI protocol (when: RLRS=0 ...

  • Page 6

    ... The flexibility of this module gives a wide choice of different protocols, including I clocks allows the use of TDA7580 as general purpose digital audio processor. A fully asynchronous sample rate converter (ASRC) is available as a peripheral prior to sending audio data out via the SAI, so that internal audio sampling rate (~36kHz and FM/AM mode) can be adapted by upconversion to any external rate ...

  • Page 7

    ... TDA7580 2 Block diagram and electrical specifications Figure 1. Block diagram HS3I CGU Oscillator Table 2. Absolute maximum ratings Symbol V DD Power supplies V DD3 Analog input or output voltage belonging to 3.3V IO ring ( DDSD Digital input or output voltage, 5V tolerant All remaining digital input or output voltage T Operating junction temperature range ...

  • Page 8

    ... Oscillator power supply (1) (GND ) OSC IF ADC power supply (1) (with G ) NDSD DAC keying and tuner clock power supply (with GND MTR . All others as V DD3 Parameter TDA7580 Min. Typ. Max. 1.7 1.80 1.9 3.15 3.30 3.45 3.15 3.30 3.45 3.15 3.30 3.45 1 ...

  • Page 9

    ... TDA7580 2.1 Pin description Figure 2. PIN connection (top view) VCMOP GNDSD GNDOSC VDDOSC VDDMTR CKREFP CKREFN AGCKEY GNDMTR Table 5. Pin description N° Name Type 1 VHI A 2 VCM A 3 VLO A 4 INP A 5 INN A 6 VCMOP - Block diagram and electrical specifications VHI ...

  • Page 10

    ... I C mode: data for main RDS I SPI slave data out or master data in for main SPI and RDS SPI data out Bit clock for Control Serial Interface and RDS TDA7580 After Notes Reset Clean ground star connected to voltage regulator ground Clean ground star ...

  • Page 11

    ... TDA7580 Table 5. Pin description (continued) N° Name Type 21 GND G 22 VDD P 23 IQSYNC B 24 IQCH1 B 25 IQCH2 B 26 IQCH3 B 27 VDDH P 28 GNDH G 29 RDS_INT B 30 RDS_CS B 31 INT I 32 ADDR_SD B 33 RESETN I 34 VDD P 35 GND G 36 TESTN I Block diagram and electrical specifications ...

  • Page 12

    ... Digital core power supply Digital core power ground Debug port clock of DSP0 (DBCK0) Debug port data input of DSP0 (DBIN0) Debug port request of DSP0 (DBRQ0) Debug port data output of DSP0 (DBOUT0) TDA7580 After Notes Reset 5V tolerant. DSP0 GPIO3. With internal Input pull-up reset [PP] 5V tolerant ...

  • Page 13

    ... TDA7580 Table 5. Pin description (continued) N° Name Type 53 GNDH G 54 VDDH P 55 DBCK1 B 56 DBIN1 B 57 DBRQ1 B 58 DBOUT1 B 59 VDD P 60 GND G 61 VDDISO P 62 GNDH G 63 VDDH P 64 VDDSD P I/O Type P: Power supply from voltage regulator G: Power ground from voltage regulator ...

  • Page 14

    ... DD3 DD3 (spec absolute value without pull up / down o DD3 (1) device ( < 0V, V > Leakage, 1μA TDA7580 Min. Typ. Max. Unit μA 1 μA 1 μA 1 μA 1 μ μA -100 -70 -40 μA -40 -30 -20 0.95 1.25 1.55 mA -6.25 -5.0 -3.75 mA 6.0 8.0 10.0 mA -10.0 -8.0 -6 ...

  • Page 15

    ... TDA7580 Table 7. Low voltage interface CMOS DC electrical characteristics (T =-40°C to 125° Symbol Parameter V Low level input voltage il V High level input voltage ih V Low level output voltage ol V High level output voltage the source/sink current under worst case conditions and reflects the name of the I/O cell according to the drive capability ...

  • Page 16

    ... Frequency stability (-20°C÷+70°C) Clock jitter Start up time Clock level (sine wave) Clock level (square wave) Clock duty cycle (square wave) Clock rise / fall time (square wave) 1. specified @ XTI pin of TDA7580 16/39 =1.7V to 1.9V Parameter Test condition 1 chip load -55°C÷125°C ± ...

  • Page 17

    ... TDA7580 Table 13. DSP core (T =-40°C to 125°C) j Symbol Parameter F Maximum DSP clock frequency dspMax Table 14. FM stereo decoder characteristics (T =-40°C to 125° 20Hz to 15KHz) Symbol Parameter a_ch Channel separation THD Total harmonic distortion (S+N)/N Signal plus noise to noise ratio MCK = 18 ...

  • Page 18

    ... IFS SLAVE=1 IFS MASTER C/SPI SLAVE C/SPI MASTER=0 Boot t t int rhd vdd3 t rsu t reson TDA7580 2 C RDS init SW download Tuner data dat t t seq tun RDS init SW download Tuner data dat t t seq tun Data ...

  • Page 19

    ... TDA7580 Table 16. SPI and I (T =-40°C to 125° Timing t Rise time of 3.3V supply vdd3 t Rise time of 1.8V supply vdd t Maximux delay for INT signal int t Minimum RESETN hold time at 0 after the start-up reson t Minimum data set-up time rsu t Minimum data hold time ...

  • Page 20

    ... Figure 6. SAI protocol (when: RLRS=0; RREL=0; RCKP=1; RDIR=0) LRCKR SCKR SDI0-1 20/39 Valid Valid t lrs sdis t sckpl =1.7V to 1.9V Description DSP LEFT RIGHT LSB(n-1) MSB(n) TDA7580 t lrh t sdih t sckph t sckr = 3.15V to 3.45V) C The DD3 load Min Typ Max 302 976 146 ...

  • Page 21

    ... TDA7580 Figure 7. SAI protocol (when: RLRS=1; RREL=0; RCKP=1; RDIR=1) LRCKR SCKR SDI0-1 Figure 8. SAI protocol (when: RLRS=0; RREL=0; RCKP=0; RDIR=0) LRCKR SCKR SDI0-1 Figure 9. SAI protocol (when: RLRS=0; RREL=1; RCKP=1; RDIR=0) LRCKR SCKR SDI0-1 LEFT MSB(n-1) LSB(n) LEFT LSB(n-1) MSB(n) LEFT ...

  • Page 22

    ... SS hold time sshold t SS pulse width ssw 22/39 Valid dtr setup hold t sssetup t t sclkl t sclk =1.7V to 1.9V DD3 Description Slave configured TDA7580 t t sshold ssw sclkh = 3.15V to 3.45V) C The load Min Typ Max Unit 1240 ns 239 365 ns 255 ns 365 ns 620 ns 620 ...

  • Page 23

    ... TDA7580 Figure 11. RDS SPI clocking scheme SS(#17) (CPOL=0,CPHA=0) SCK(#20) (CPOL=0,CPHA=1) SCK(#20) SCK(#20) (CPOL=1,CPHA=0) (CPOL=1,CPHA=1) SCK(#20) MISO(#19) MOSI(#18) MSB RDS SPI interface 23/39 ...

  • Page 24

    ... SS setup time sssetup t SS hold time sshold t SS pulse width ssw 24/39 =1.7V to 1.9V 3.15V to 3.45V DD3 Valid dtr setup hold t sssetup t sclkl t sclk Description TDA7580 load t t sshold ssw t sclkh Min Typ Max Unit 184 184 238 88 119 65 65 119 ...

  • Page 25

    ... TDA7580 Figure 13. BSPI clocking scheme SS(#17) (CPOL=0,CPHA=0) SCK(#20) (CPOL=0,CPHA=1) SCK(#20) SCK(#20) (CPOL=1,CPHA=0) (CPOL=1,CPHA=1) SCK(#20) MISO(#19) MOSI(#18) MSB BSPI interface 25/39 ...

  • Page 26

    ... Slave data out setup time hold Note DSP master clock cycle time = 1/F DSP 26/39 =1.7V to 1.9V 3.15V to 3.45V DD3 3 I lines of 20pF M2 M3 256 cycles of 74.1MHz mbco t mbcs t mbcc Description DSP TDA7580 . The values on the load sdos Min Typ Max Unit 107.95 107. ...

  • Page 27

    ... TDA7580 timing Figure 16. DSP and RDS I 2 Table 21 BUS timing table (T =-40°C to 125° Symbol Parameter F SCLl clock frequency SCL Bus free between a stop and start t BUF condition Hold time (repeated) START condition. t After this period, the first clock pulse is ...

  • Page 28

    ... Functional description 8 Functional description The TDA7580 IC offers a solution for high performance FM/AM car radio receivers. The high processing power allows audio processing of both internal and external audio source. The processing engine is based on a 24bit programmable DSP, with separate banks of program and data RAMs. A number of hardware modules (peripherals) help in the algorithm implementation of channel equalization and FM/AM baseband post processing ...

  • Page 29

    ... TDA7580 8.2 DSP peripherals ● Clock generation unit (CGU) ● Stereo decoder (HWSTER) ● Serial audio interface (SAI) ● Tuner AGC keying DAC (KEYDAC) ● Programmable I/O interface (I ● Asynchronous sample rate converter (ASRC) ● IF band pass sigma delta modulator (IFADC) ● ...

  • Page 30

    ... When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI 30/ bus bus has its own unique address whether CPU the DSP and RDS, which have different internal TDA7580 2 C one. DSP and RDS ...

  • Page 31

    ... High speed serial synchronous interface (HS The high speed serial synchronous interface is a module to send and receive data at high rate (up to 9.25Mbit/s per channel) in order to exchange data between 2 separate TDA7580 chip. The exchanged data are related to signals that are used to increase reception quality in car radio systems, which make use of antenna diversity based upon two separate antenna and tuner sections ...

  • Page 32

    ... It can be used to demodulate PM, AM and FM modulated signals. The detection is performed using a high accuracy CORDIC algorithm, working essentially as a cartesian to polar transformer. Four CORDICs are available to allow concurrent software calls. 32/39 TDA7580 2 C/SPI ...

  • Page 33

    ... Figure 18. Radio mode with external master audio device TDA7580 external digital audio device is connected externally as a digital audio master, and the internal TDA7580 sample rate converter is responsible for the conversion from internal 36kHz to the external audio rate TST3_LRCKR 46 45 TST2_SCKR 44 LRCK_LRCKT 43 SCLK_SCKT SDO0 42 41 Fs=36kHz 40 TST1_SDI1 39 ...

  • Page 34

    ... The 2 stereo channel serial audio interface of the TDA7580 chip allows a very flexible application in which external audio source/sinks can be connected. The example shows an external CD player digital output giving the main Fs audio rate of the whole system. This rate is also the one of the external DACs and an ADC, being configured as slave ...

  • Page 35

    ... TDA7580 9.1 Electrical application scheme The following application diagram is only an example. For real application setup necessary to refer to the application notes. Figure 20. Application diagram example Note: VCMOP capacitor (4.7uF) is only needed for CA silicon. This is needed to be consistent with "pin description " in Table 6 ...

  • Page 36

    ... Package marking 10 Package marking Figure 21. Package marking 36/39 TDA7580 ...

  • Page 37

    ... TDA7580 11 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

  • Page 38

    ... Included separated specification for the 2 SPI (BSPI and RDS-SPI). Upgraded all tables with temperature range and electrical / timing 3 parameters. Changed description of PIN 6 in PIN description table. Added new sub section titled AM/FM Detector (CORDIC). 4 Updated all tables. 5 Package changed, layout and text modifications TDA7580 Changes ...

  • Page 39

    ... TDA7580 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...