SI4330-B1-FMR Silicon Laboratories Inc, SI4330-B1-FMR Datasheet - Page 23

• Manufacturer Part Number: SI4330-B1-FMR
• Description: IC RX ISM 240-960MHZ 20VQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4330-B1-FMR

• Frequency: 240MHz ~ 960MHz
• Sensitivity: -121dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 18.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

3.5. Frequency Control
For calculating the necessary frequency register settings it is recommended that customers use Silicon Labs’
Wireless Design Suite (WDS) or the EZRadioPRO Register Calculator worksheet (in Microsoft Excel) available on
the product website. These methods offer a simple method to quickly determine the correct settings based on the
application requirements. The following information can be used to calculated these values manually.
3.5.1. Frequency Programming
In order to receive an RF signal, the desired channel frequency, f
that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency
is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3
order) ΔΣ modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the
desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer
part (N) and a fractional part (F). In a generic sense, the output frequency of the synthesizer is as follows:
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset
(fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer,
FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is
discussed further in "3.5.4. Frequency Offset Adjustment" on page 26. Also, a fixed offset can be added to fine-
tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0]
register will determine the fractional component. The equation for selection of the carrier frequency is shown
below:
The integer part (N) is determined by fb[4:0]. Additionally, the frequency can be halved by connecting a ÷2 divider
to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band
Select." This effectively partitions the entire 240–960 MHz frequency range into two separate bands: High Band
(HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is
written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown
in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band.
After selection of the fb (N) the fractional component may be solved with the following equation:
fb and fc are the actual numbers stored in the corresponding registers.
Add R/W Function/Description
73
74
75
76
77
R/W
R/W
R/W Frequency Band Select Reserved
R/W
R/W
Frequency Offset 1
Frequency Offset 2
Nominal Carrier
Nominal Carrier
Frequency 1
Frequency 0
fc
f
[
15
carrier
:
] 0
Reserved Reserved Reserved Reserved Reserved Reserved fo[9] fo[8]


fc[15]
10
fo[7]
fc[7]
f
D7
carrier

 

MHz
10
MHz

f
( *
OUT
10
sbsel
fc[14]
fo[6]
fc[6]
hbsel
D6
f
( *
MHz
carrier

hbsel
10
Rev 1.0

MHz

) 1
(
fc[13]
hbsel
fo[5]
fc[5]
hbsel
( *
D5

) 1

fb
(

[
N
: 4

fb
carrier
) 1

fc[12]
] 0
[
fo[4]
fb[4]
fc[4]
D4
: 4
F


(
)
, must be programmed into the Si4330. Note
] 0
N
24



24
F
fc[11]
fc
fo[3]
fb[3]
fc[3]
)
64000
D3

 

[
15
*
64000
:
] 0
)
fc[10]
fo[2]
fb[2]
fc[2]
D2
Si4330-B1
fo[1] fo[0]
fb[1] fb[0]
fc[9] fc[8]
fc[1] fc[0]
D1
D0 POR Def.
BBh
00h
00h
35h
80h
23
rd