SI4330-B1-FMR Silicon Laboratories Inc, SI4330-B1-FMR Datasheet - Page 33

• Manufacturer Part Number: SI4330-B1-FMR
• Description: IC RX ISM 240-960MHZ 20VQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4330-B1-FMR

• Frequency: 240MHz ~ 960MHz
• Sensitivity: -121dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 18.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access
Control" through “Register 39h. Synchronization Word 0,” on page 99 and “Register 3Fh. Check Header 3,” on
page 100 through “Register 4Bh. Received Packet Length,” on page 104 control the configuration, status, and
decoded RX packet data for Packet Handling.
The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable
lengths to accommodate different applications. The most common CRC polynominals are available for selection.
An overview of the packet handler configuration registers is shown in Table 13.
6.3. Packet Handler RX Mode
6.3.1. Packet Handler Disabled
When the packet handler is disabled certain fields in the received packet are still required. Proper modem
operation requires preamble and sync when the FIFO is being used, as shown in Figure 14. Bits after sync will be
treated as raw data with no qualification. This mode allows for the creation of a custom packet handler when the
automatic qualification parameters are not sufficient. Manchester encoding is supported but data whitening, CRC,
and header checks are not
6.3.2. Packet Handler Enabled
When the packet handler is enabled, all the fields of the packet structure need to be configured. The receive FIFO
can be configured to handle packets of fixed or variable length with or without a header. If multiple packets are
desired to be stored in the FIFO, then there are options available for the different fields that will be stored into the
FIFO. Figure 15 demonstrates the options and settings available when multiple packets are enabled. Figure 16
demonstrates the operation of fixed packet length and correct/incorrect packets.
Figure 12. Required RX Packet Structure with Packet Handler Disabled
Preamble
1- 512 Bytes
Preamble
1-4 Bytes
Figure 11. Packet Structure
SYNC
Rev 1.0
Data
DATA
0 or 2
Bytes
Si4330-B1
CRC
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