SI4330-B1-FMR Silicon Laboratories Inc, SI4330-B1-FMR Datasheet - Page 54

• Manufacturer Part Number: SI4330-B1-FMR
• Description: IC RX ISM 240-960MHZ 20VQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4330-B1-FMR

• Frequency: 240MHz ~ 960MHz
• Sensitivity: -121dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 18.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Add
0C
0D
1C
1D
01
02
03
04
05
06
07
08
09
0A
0B
0E
0F
10
12
13
14
15
16
17
18
19
1A
1B
1E
1F
20
21
22
23
24
25
26
27
11
Si4330-B1
12. Register Table and Descriptions
54
R/W
R/W
R/W
R/W Operating & Function Control 1
R/W Operating & Function Control 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Low-Duty Cycle Mode Duration
R/W Low Battery Detector Threshold
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
Clock Recovery Oversampling
Received Signal Strength Indi-
AFC Loop Gearshift Override
Clock Recovery Timing Loop
Clock Recovery Timing Loop
Microcontroller Output Clock
ADC Sensor Amplifier Offset
Temperature Sensor Control
Temperature Value Offset
Clock Recovery Gearshift
RSSI Threshold for Clear
Wake-Up Timer Period 1
Wake-Up Timer Period 2
Wake-Up Timer Period 3
Clock Recovery Offset 2
Clock Recovery Offset 1
Clock Recovery Offset 0
Wake-Up Timer Value 1
Wake-Up Timer Value 2
Crystal Oscillator Load
I/O Port Configuration
Battery Voltage Level
GPIO0 Configuration
GPIO1 Configuration
GPIO2 Configuration
AFC Timing Control
ADC Configuration
IF Filter Bandwidth
Interrupt Enable 1
Interrupt Enable 2
Channel Indicator
Interrupt Status 1
Interrupt Status 2
Function/Desc
Device Version
Device Status
Capacitance
ADC Value
Override
Gain 1
Gain 0
Ratio
cator
dwn3_bypass
swait_timer[1]
adcstart/adc-
gpio0drv[1]
gpio1drv[1]
gpio2drv[1]
tsrange[1]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
rxosr[10]
enswdet
antdiv[2]
ncoff[15]
crgain[7]
wtm[15]
rssith[7]
tvoffs[7]
rxosr[7]
xtalshft
wtv[15]
ncoff[7]
wtm[7]
iswdet
enfferr
swres
adc[7]
wtv[7]
rssi[7]
afcbd
ldc[7]
ffovfl
done
ifferr
D7
0
0
Table 17. Register Descriptions
swait_timer[0]
gpio0drv[0]
gpio1drv[0]
gpio2drv[0]
enpreaval
tsrange[0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
adcsel[2]
antdiv[1]
extitst[2]
ncoff[14]
crgain[6]
ipreaval
ndec[2]
rssith[6]
tvoffs[6]
wtm[14]
rxosr[6]
rxosr[9]
wtv[14]
ncoff[6]
wtm[6]
adc[6]
wtv[6]
rssi[6]
enlbd
enafc
xlc[6]
ldc[6]
ffunfl
D6
0
0
Rev 1.0
enpreainval
afcgearh[2]
Reserved
ipreainval
Reserved
Reserved
Reserved
Reserved
Reserved
adcsel[1]
ncoff[13]
crgain[5]
antdiv[0]
extitst[1]
shwait[2]
entsoffs
tvoffs[5]
wtm[13]
ndec[1]
crfast[2]
rssith[5]
rxosr[5]
rxosr[8]
ncoff[5]
wtv[13]
wtm[5]
rxffem
adc[5]
clkt[1]
wtv[5]
rssi[5]
xlc[5]
ldc[5]
pup0
pup1
pup2
enwt
D5
0
0
afcgearh[1]
rxncocomp
enrxffafull
Reserved
adcsel[0]
ncoff[12]
crgain[4]
extitst[0]
shwait[1]
headerr
gpio0[4]
gpio1[4]
gpio2[4]
entstrim
tvoffs[4]
wtm[12]
ndec[0]
crfast[1]
rssith[4]
irxffafull
x32ksel
rxosr[4]
ncoff[4]
wtv[12]
stallctrl
wtm[4]
vbat[4]
rxmpk
adc[4]
enrssi
clkt[0]
wtv[4]
lbdt[4]
rssi[4]
wtr[4]
ldc[4]
xlc[4]
vc[4]
irssi
D4
Data
afcgearh[0] 1p5 bypass
Reserved
Reserved
adcoffs[3]
reserved
adcref[1]
ncoff[19]
ncoff[11]
crgain2x
crgain[3]
gpio0[3]
gpio1[3]
gpio2[3]
tstrim[3]
shwait[0]
crfast[0]
tvoffs[3]
wtm[11]
rssith[3]
rxosr[3]
ncoff[3]
wtv[11]
vbat[3]
wtm[3]
filset[3]
enwut
adc[3]
wtv[3]
lbdt[3]
rssi[3]
enext
xlc[3]
wtr[3]
ldc[3]
vc[3]
enlfc
itsdo
iwut
iext
D3
crgain[10]
Reserved
Reserved
adcoffs[2]
reserved
adcref[0]
crslow[2]
ncoff[18]
ncoff[10]
crgain[2]
anwait[2]
gpio0[2]
gpio1[2]
gpio2[2]
tstrim[2]
tvoffs[2]
wtm[10]
rssith[2]
rxosr[2]
ncoff[2]
mclk[2]
wtv[10]
wtm[2]
vbat[2]
enldm
adc[2]
filset[2]
wtv[2]
lbdt[2]
rssi[2]
enlbd
wtr[2]
ldc[2]
xlc[2]
vc[2]
rxon
dio2
ilbd
D2
adcgain[1]
enpkvalid
enchiprdy
adcoffs[1]
crslow[1]
anwait[1]
ncoff[17]
crgain[9]
crgain[1]
gpio0[1]
gpio1[1]
gpio2[1]
tstrim[1]
ichiprdy
tvoffs[1]
rssith[1]
ipkvalid
mclk[1]
rxosr[1]
ncoff[9]
ncoff[1]
wtm[1]
vbat[1]
wtm[9]
filset[1]
cps[1]
adc[1]
wtv[9]
wtv[1]
lbdt[1]
matap
rssi[1]
ffclrrx
wtr[1]
xlc[1]
ldc[1]
vc[1]
pllon
dio1
D1
encrcerror
adcgain[0]
adcoffs[0]
Reserved
crslow[0]
ncoff[16]
crgain[8]
crgain[0]
icrcerror
anwait[0]
gpio0[0]
gpio1[0]
gpio2[0]
tstrim[0]
tvoffs[0]
ph0size
rssith[0]
rxosr[0]
ncoff[8]
ncoff[0]
mclk[0]
wtm[8]
wtm[0]
vbat[0]
filset[0]
cps[0]
adc[0]
lbdt[0]
rssi[0]
enpor
wtv[8]
wtv[0]
xlc[0]
wtr[0]
ldc[0]
vc[0]
xton
dio0
ipor
D0
Default
POR
AEh
06h
00h
03h
01h
00h
7Fh
06h
00h
00h
00h
00h
00h
00h
20h
00h
03h
00h
01h
00h
14h
40h
0Ah
03h
64h
01h
47h
02h
8Fh
1Eh
01h
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