CYWUSB6934-48LFXC Cypress Semiconductor Corp, CYWUSB6934-48LFXC Datasheet - Page 13

• Manufacturer Part Number: CYWUSB6934-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Type: Transceiverr

Specifications of CYWUSB6934-48LFXC

• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: HID, PC, Peripheral Gaming Devices
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2483 MHz
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1624

Table 11. Receive SERDES Data A
Table 12. Receive SERDES Valid A
Figure 9. Receive SERDES Data B
Table 13. Receive SERDES Valid B
Document 38-16007 Rev. *J
7:0
7:0 Valid
7:0 Data
7:0
Bit
Bit
Bit Name
Bit
Valid
Data
Name
Name
Name
7
7
7
7
Addr: 0x0A
Addr: 0x0B
Addr: 0x0C
Addr: 0x09
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that
the corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B
register (Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C).
This register is read-only.
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by
bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that
the corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES
Data A register (Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg
0x0C). This register is read-only.
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by
bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
6
6
6
6
5
5
5
5
REG_RX_VALID_B
REG_RX_VALID_A
REG_RX_DATA_A
REG_RX_DATA_B
4
4
4
4
Valid
Valid
Data
Data
Description
Description
Description
Description
3
3
3
3
2
2
2
2
1
1
1
1
CYWUSB6934
CYWUSB6932
Default: 0x00
Default: 0x00
Default: 0x00
Default: 0x00
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