CYWUSB6934-48LFXC Cypress Semiconductor Corp, CYWUSB6934-48LFXC Datasheet - Page 20

• Manufacturer Part Number: CYWUSB6934-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Type: Transceiverr

Specifications of CYWUSB6934-48LFXC

• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: HID, PC, Peripheral Gaming Devices
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2483 MHz
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1624

Table 27. Crystal Adjust
Table 28. VCO Calibration
Table 29. Reg Power Control
Document 38-16007 Rev. *J
7
6
5:0 Crystal Adjust
7:6 VCO Slope Enable
5:0 Reserved
7
6:0
Bit
Bit
Bit
Reg Power
Reserved
Control
Reserved
Clock Output
Disable
(Write-Only)
Reg Power
Control
Reserved
VCO Slope Enable
7
7
7
Name
Addr: 0x2E
Addr: 0x24
Addr: 0x26
Name
Name
Clock Output
When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable
writes to Reg 0x2E. The application MCU must set this bit during initialization.
These bits are reserved and should be written with zeroes.
Disable
6
6
6
The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance
automatically added to the VCO.
11 = –5/+5 VCO adjust. The application MCU must configure this option during initialization.
10 = –2/+3 VCO adjust.
01 = Reserved.
00 = No VCO adjust.
These bits are undefined for read operations.
These bits are reserved and should be written with zeroes.
This bit is reserved and should be written with zero.
The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin.
1 = No 13-MHz clock driven externally.
0 = 13-MHz clock driven externally.
If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on
channels 5+13 n . By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the
13-MHz clock, but it interfere with every 13th channel beginning with 2.405GHz channel. Therefore, it is
recommended that the 13-MHz clock output pin be disabled when not in use.
The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal.
Each increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total
range is 8.5 pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an
additional 1–2 pF.
5
5
5
REG_CRYSTAL_ADJ
4
4
4
REG_VCO_CAL
REG_PWR_CTL
Reserved
Description
Description
Description
3
3
3
Crystal Adjust
Reserved
2
2
2
1
1
1
CYWUSB6934
CYWUSB6932
Default: 0x00
Default: 0x00
Default: 0x00
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