T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 31

• Manufacturer Part Number: T48C862M-R4-TNQ
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNQ

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Figure 27. Example of I/O Addressing
4551C–4BMCU–01/04
program code
Addr.(ASW)
Addr.(Mx)
Addr.(SPort) = Subport address
Prim._Data
Aux._Data
Prim._Data(lo) = Data to be written into Auxiliary Register (low nibble)
Example of
Module ASW
qFORTH
Auxiliary Switch
Primary Reg.
Module
= Auxiliary Switch Module address
= Module Mx address
= Data to be written into Primary Register
= Data to be written into Auxiliary Register
1 Addr. (SPort) Addr. (M1)
1 Addr. (SPort) Addr. (M1) OUT
1 Addr. (SPort) Addr. (M1) OUT
2
1 Addr. (SPort) Addr. (M1) OUT
2
2
2 SPort _Data
2 SPort _Data(lo) Addr. (M1) OUT
2 SPort _Data(hi) Addr. (M1) OUT
(Address Pointer)
Subaddress Reg.
(Subport Register Write Byte)
(Subport Register Read Byte)
(Subport Register Write)
Indirect Subport Access
(Subport Register Read)
1
Module M1
Addr. (M1) IN (hi)
Addr. (M1) IN (lo)
Addr. (M1) OUT
Addr. (M1)
Primary Reg.
Subport Eh
Subport Fh
Subport 0
Subport 1
Bank of
IN
OUT
2
5
4 Addr. (M2) Addr. (ASW) OUT
4 Addr. (M2) Addr. (ASW) OUT
4
5
5
3
3
5
I/O bus
Prim._Data(hi) = Data to be written into Auxiliary Register (high nibble)
SPort_Data(lo) = Data to be written into SubPort (low nibble)
SPort_Data(hi) = Data to be written into SubPort (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
(Auxiliary Register Write Byte)
Aux._Data
Addr. (M2)
Aux._Data (lo) Addr. (M2)
Aux._Data (hi) Addr. (M2)
Prim._Data Addr. (M2)
(Auxiliary Register Read)
(Primary Register Write)
(Auxiliary Register Write)
(Primary Register Read)
Aux. Reg.
Dual Register Access
5
4
Module M2
Addr. (ASW)
Addr. (M2)
Addr. (M2)
Addr. (M2)
T48C862-R4 [Preliminary]
Primary Reg.
OUT
OUT
IN
IN
3
OUT
OUT
OUT
6 Prim._Data Addr.(M3) OUT
6
to other modules
Single Register Access
(Primary Register Write)
(Primary Register Read)
Primary Reg.
Module M3
Addr. (M3)
6
IN
31