T48C862M-R4-TNS Atmel, T48C862M-R4-TNS Datasheet
T48C862M-R4-TNS
Specifications of T48C862M-R4-TNS
Related parts for T48C862M-R4-TNS
T48C862M-R4-TNS Summary of contents
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Features • Single Package Fully-integrated 4-bit Flash Microcontroller with RF Transmitter • Low Power Consumption in Sleep Mode (< 1 µA Typically) • Maximum Output Power (10 dBm) with Low Supply Current (9.5 mA Typically) • 2 4.0 ...
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Pin Configuration Figure 2. Pinning SSO24 Pin Description: RF Part Pin Symbol Function 1 XTAL Connection for crystal 2 VS Supply voltage 3 GND Ground 4 ENABLE Enable input T48C862-R4 [Preliminary] 2 XTAL 1 24 ANT1 ANT2 ...
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Pin Description: RF Part (Continued) Pin Symbol Function Clock output signal for microcontroller, 21 CLK the clock output frequency is set by the crystal to f Switches on power amplifier, used for 22 PA_ENABLE ASK modulation 23 ANT2 Emitter of ...
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UHF ASK/FSK Transmitter Block Features • Integrated PLL Loop Filter • ESD Protection (4 kV HBM/200 V MM, Except Pin HBM/100 V MM) also at ANT1/ANT2 • Maximum Output Power (10 dBm) with Low Supply Current (9.5 ...
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Figure 3. Block Diagram CLK PA_ENABLE ANT2 ANT1 OSC2 OSC1 NRESET BP10 BP13 BP20/NTE BP21 BP22 BP23 4551C–4BMCU–01/04 T48C862 Power up / down PFD VCO PLL Brown-out protect. RC ...
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General Description Functional Description ASK Transmission FSK Transmission T48C862-R4 [Preliminary] 6 The fully-integrated PLL transmitter that allows particularly simple, low-cost RF minia- ture transmitters to be assembled. The VCO is locked to 32 crystal is needed for a 433.92 MHz ...
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CLK Output Clock Pulse Take Over Output Matching and Power Setting 4551C–4BMCU–01/04 Figure 4. Tolerances of Frequency Modulation ~ XTAL Using C = 9.2 pF ±2 6.8 pF ±5%, a switch port with C 4 ...
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Application Circuit T48C862-R4 [Preliminary] 8 Figure 5. Output Power Measurement ANT1 Z Lopt ANT2 ~ For the supply-voltage blocking capacitor C (see Figure 6 on page 9 and Figure 7 on page 10). C antenna to the power amplifier where ...
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Figure 6. ASK Application Circuit C4 XTAL 1 XTAL GND 3 ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 11 VSS 12 4551C–4BMCU–01/04 T48C862-R4 [Preliminary] XTO VCO PA ...
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Figure 7. FSK Application Circuit C4 XTAL 1 C5 XTAL GND 3 ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 11 VSS 12 T48C862-R4 [Preliminary] 10 XTO VCO ...
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Figure 8. ESD Protection Circuit VS GND Absolute Maximum Ratings: RF Part Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at ...
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Electrical Characteristics (Continued +125 C unless otherwise specified. S amb Typical values are given 3.0 V and T S Parameters Output power Output power variation ...
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... EEPROM block during programming. The configuration is down- loaded to the I/Os with every power-on reset. The microcontroller block is a member of Atmel’s family of 4-bit single-chip microcontrol- lers. Instead of ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal oscillators ...
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Reset Function MARC4 Architecture General Description Components of MARC4 Core Program Memory T48C862-R4 [Preliminary] 14 During each reset (power-on or brown-out), the I/O configuration is deleted and reloaded with the data from the configuration memory. This leads to a slightly ...
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RAM Expression Stack Return Stack 4551C–4BMCU–01/04 The corresponding memory map is shown in Figure 10. Look-up tables of constants can also be held in ROM and are accessed via the microcontrollers’ built-in table instruction. Figure 10. ROM Map of the ...
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Registers Program Counter (PC) T48C862-R4 [Preliminary] 16 Figure 11. RAM Map RAM (256 x 4-bit) Autosleep FCh TOS-1 RP 04h 00h The microcontroller has seven programmable registers and one condition code register (see Figure 12). The program ...
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RAM Address Registers Expression Stack Pointer (SP) The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the Return Stack Pointer (RP) RAM Address Registers (X and Y) Top of Stack (TOS) Condition Code Register (CCR) Carry/Borrow ...
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ALU I/O Bus Instruction Set Interrupt Structure T48C862-R4 [Preliminary] 18 The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the ...
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Interrupt Processing Interrupt Latency Figure 14. Interrupt Handling INT3 4 3 INT3 active Main / Autosleep 4551C–4BMCU–01/04 For processing the eight interrupt levels, the microcontroller includes an interrupt con- troller with two 8-bit wide ...
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Table 1. Interrupt Priority Interrupt Priority INT0 Lowest INT1 | INT2 | INT3 | INT4 | INT5 | INT6 INT7 Highest Table 2. Hardware Interrupts Interrupt Register INT1 INT2 INT3 INT4 T3CM1 INT5 T3CM2 INT6 INT7 Software Interrupts Hardware Interrupts ...
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Master Reset Power-on Reset and Brown-out Detection 4551C–4BMCU–01/04 The master reset forces the CPU into a well-defined condition unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a ...
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Watchdog Reset External Clock Supervisor Voltage Monitor T48C862-R4 [Preliminary power-on reset pulse is generated (1.7 V). A brown-out reset pulse is generated when V age threshold. Two values for the brown-out voltage threshold are programmable ...
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Voltage Monitor Control/Status Register 4551C–4BMCU–01/04 Figure 17. Voltage Monitor BP41/ IN VMI VMC : VM2 VMST : Bit 3 VMC: Write VM2 VMST: Read – VM2: V oltage monitor M ode bit 2 VM1: V oltage monitor M ode bit ...
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Clock Generation Clock Module T48C862-R4 [Preliminary] 24 Figure 18. Internal Supply Voltage Supervisor Low threshold VMS = 1 Middle threshold High threshold V DD 3.0 V 2.6 V 2.2 V Figure 19. External Input Voltage Supervisor VMI Negative slope VMS ...
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Oscillator Circuits and External Clock Input Stage RC-oscillator 1 Fully Integrated 4551C–4BMCU–01/04 Figure 20. Clock Module Ext. clock OSC1 Osci ExOu ExI Stop * RC oscillator2 RCOut2 R Trim Stop 4-MHz oscillator Osci 4Out n Oscou Stop ...
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External Input Clock RC-oscillator 2 with External Trimming Resistor T48C862-R4 [Preliminary] 26 Figure 21. RC-oscillator 1 The OSC1 or OSC2 (mask option) can be driven by an external clock source provided it meets the specified duty cycle, rise and fall ...
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Oscillator 32-kHz Oscillator 4551C–4BMCU–01/04 Figure 23. RC-oscillator ext OSC1 OSC2 The microcontroller block 4-MHz oscillator options need a crystal or ceramic resonator connected to the OSC1 and OSC2 pins to establish oscillation. All the necessary ...
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Clock Management Clock Management Register (CM) T48C862-R4 [Preliminary] 28 Figure 26. 32-kHz Crystal Oscillator OSC1 XTAL 32 kHz OSC2 * Configurable The clock management register controls the system clock divider and synchronization stage. Writing to this register triggers the synchronization ...
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System Configuration Register (SC) Power-down Modes 4551C–4BMCU–01/04 Bit 3 Bit 2 SC: write BOT – BOT Brown-Out Threshold BOT = 1, low brown-out voltage threshold (1.7 V) BOT = 0, high brown-out voltage threshold (2.0 V) OS1 Oscillator Select 1 ...
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Peripheral Modules Addressing Peripherals T48C862-R4 [Preliminary] 30 The microcontroller block has various power-down modes. During the sleep mode the clock for the microcontroller block core is stopped. With the NSTOP bit in the clock man- agement register (CM ...
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Figure 27. Example of I/O Addressing Module ASW (Address Pointer) Subaddress Reg. Auxiliary Switch Module 1 Primary Reg. Indirect Subport Access (Subport Register Write) 1 Addr. (SPort) Addr. (M1) OUT 2 SPort _Data (Subport Register Read) 1 Addr. (SPort) Addr. ...
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Table 9. Peripheral Addresses Port Address Name 1 P1DAT 2 P2DAT Auxiliary P2CR 3 SC CWD Auxiliary CM 4 P4DAT Auxiliary P4CR 5 P5DAT Auxiliary P5CR 6 P6DAT Auxiliary P6CR 7 T12SUB Subport address 0 T2C 1 T2M1 2 T2M2 ...
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Bi-directional Ports Bi-directional Port 1 4551C–4BMCU–01/04 With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 ...
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Bi-directional Port 2 T48C862-R4 [Preliminary] 34 Figure 28. Bi-directional Port 1 I/O Bus (Data out P1DATy R Reset (Direction) OUT Master reset As all other bi-directional ports, this port includes a bitwise programmable ...
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Port 2 Data Register (P2DAT) Port 2 Control Register (P2CR) Bi-directional Port 5 4551C–4BMCU–01/04 Bit 3 * Bit 2 Bit 1 P2DAT3 P2DAT2 P2DAT1 * Bit 3 -> MSB, Bit 0 -> LSB Bit 3 Bit 2 Bit 1 P2CR3 ...
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Port 5 Data Register (P5DAT) Port 5 Control Register (P5CR) Byte Write T48C862-R4 [Preliminary] 36 Figure 30. Bi-directional Port 5 I/O Bus (Data out) I/O Bus D Q P5DATy S Master reset IN enable Figure 31. Port 5 External Interrupts ...
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Table 11. Port 5 Control Register Auxiliary Address: "5"hex, First Write Cycle Code Function – BP50 in input mode interrupt disabled – BP50 in input mode rising edge ...
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Port 4 Data Register (P4DAT) Port 4 Control Register (P4CR) Byte Write Bi-directional Port 6 T48C862-R4 [Preliminary] 38 Bit 3 Bit 2 Bit 1 P4DAT3 P4DAT2 P4DAT1 Bit 3 First write cycle P41M2 Bit 7 Second write cycle P43M2 P4xM2, ...
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Port 6 Data Register (P6DAT) Port 6 Control Register (P6CR) Universal Timer/Counter/ Communication Module (UTCM) 4551C–4BMCU–01/04 Bit 3 Bit 2 Bit 1 P6DAT3 – – Bit 3 Bit 2 Bit 1 P63M2 P63M1 P60M2 P6xM2, P6xM1 – Port 6x Interrupt ...
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Timer 1 T48C862-R4 [Preliminary] 40 Figure 33. UTCM Block Diagram SYSCL from clock module SUBCL MUX T1OUT T3I MUX TOG3 MUX POUT T2I MUX DCG TOG2 MUX The Timer interval timer which can be used to generate ...
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Figure 35. Timer 1 and Watchdog T1C1 T1RM T1C2 T1C1 T1C0 3 Write of the T1C1 register Decoder RES CL1 CL Decoder WDL WDR WDT1 WDT0 WDC 4551C–4BMCU–01/04 This timer starts running automatically after any power-on reset! If the watchdog ...
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Timer 1 Control Register 1 (T1C1) T48C862-R4 [Preliminary] 42 Bit 3 * Bit 2 Bit 1 T1RM T1C2 T1C1 * Bit 3 -> MSB, Bit 0 -> LSB T1RM T imer 1 R estart M ode T1RM = 0, write ...
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Timer 1 Control Register 2 (T1C2) Watchdog Control Register (WDC) 4551C–4BMCU–01/04 Bit 3 * Bit 2 Bit 1 – T1BP T1CS * Bit 3 -> MSB, Bit 0 -> LSB T1BP T imer 1 SUBCL assed T1BP ...
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Timer 2 T48C862-R4 [Preliminary] 44 8-/12-bit Timer for: • Interrupt, square-wave, pulse and duty cycle generation • Baud-rate generation for the internal shift register • Manchester and Biphase modulation together with the SSI • Carrier frequency generation and modulation together ...
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Timer 2 Modes Mode 1: 12-bit Compare Counter Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler 4551C–4BMCU–01/04 Figure 36. Timer 2 P4CR T2I SYSCL CL2/1 T1OUT 4-bit Counter 2/1 TOG3 SCL RES OVF1 POUT T2C Compare 2/1 CM1 T2CO1 ...
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Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler Timer 2 Output Modes T48C862-R4 [Preliminary] 46 Figure 39. 4-/8-bit Compare Counter T2I CL2/2 DCG 8-bit counter SYSCL 8-bit compare 8-bit register P4CR P41M2, 1 T2D1, 0 TOG3 CL2/1 T1OUT 4-bit ...
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Timer 2 Output Signals Timer 2 Output Mode 1 4551C–4BMCU–01/04 Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 41. Interrupt Timer/Square Wave Generator – the Output Toggles with Each Edge Compare Match ...
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Timer 2 Output Mode 2 Timer 2 Output Mode 3 T48C862-R4 [Preliminary] 48 Toggle Mode Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 43. Pulse Generator – the Timer Toggles with Timer Overflow ...
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Timer 2 Output Mode 4 Timer 2 Output Mode 5 Timer 2 Output Mode 7 4551C–4BMCU–01/04 Biphase Modulator: Timer 2 modulates the SSI internal data output (SO) to Biphase code Figure 46. Biphase Modulation TOG2 Bit ...
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Timer 2 Registers Timer 2 Control Register (T2C) Timer 2 Mode Register 1 (T2M1) T48C862-R4 [Preliminary] 50 Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function. All registers ...
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Duty Cycle Generator 4551C–4BMCU–01/04 Table 17. Timer 2 Duty Cycle Bits T2D1 T2D0 Function of Duty Cycle Generator (DCG Bypassed (DCGO0 Duty cycle 1/1 (DCGO1 Duty cycle 1/2 (DCGO2 Duty cycle 1/3 ...
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Timer 2 Mode Register 2 (T2M2) Timer 2 Compare and Compare Mode Registers T48C862-R4 [Preliminary] 52 Bit 3 Bit 2 Bit 1 T2TOP T2OS2 T2OS1 T2TOP T imer 2 T oggle O utput P reset This bit allows the programmer ...
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Timer 2 Compare Mode Register (T2CM) Timer 2 COmpare Register 1 (T2CO1) Timer 2 COmpare Register 2 (T2CO2) Byte Write 4551C–4BMCU–01/04 Bit 3 Bit 2 Bit 1 T2OTM T2CTM T2RM T2OTM T imer 2 O verflow T oggle M ask ...
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Timer 3 Features Figure 50. Timer 3 TOG2 Capture register CL3 RES 8-bit counter 8-bit comparator Compare register 1 Compare register 2 T48C862-R4 [Preliminary] 54 • Two Compare Registers • Capture Register • Edge Sensitive Input with Zero Cross Detection ...
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Timer/Counter Modes 4551C–4BMCU–01/04 Timer 3 consists of an 8-bit up-counter with two compare registers and one capture reg- ister. The timer can be used as event counter, timer and signal generator. Its output can be programmed as modulator and demodulator ...
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Figure 51. Counter 3 Stage TOG2 Capture register CL3 RES 8-bit counter 8-bit comparator Compare register 1 Compare register 2 Timer 3 – Mode 1: Timer/Counter T48C862-R4 [Preliminary] 56 T3I Control D T3SM1 NQ CM31 C31 Control C32 CM32 NQ ...
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Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) 4551C–4BMCU–01/04 Figure 52. Counter Reset with Each Compare Match T3R Counter 3 CM31 CM32 INT5 T3O Figure 53. Counter Reset ...
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Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2) Timer 3 – Mode 4: Timer/Counter Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) Timer 3 Modulator/Demodulator Modes Timer ...
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Timer 3 – Mode 7: Carrier Frequency Burst Modulation Controlled by SSI Internal Output (SO) Timer 3 – Mode 8: FSK Modulation with Shift Register Data (SO) Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register 4551C–4BMCU–01/04 The ...
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Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation Timer 3 – Mode 11: Biphase Demodulation T48C862-R4 [Preliminary] 60 For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by ...
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Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I) Timer 3 Modulator for Carrier Frequency Burst Modulation Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals 4551C–4BMCU–01/04 The counter is driven by an internal clock source and an ...
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Timer 3 Registers Timer 3 Mode Register (T3M) T48C862-R4 [Preliminary] 62 Bit 3 Bit 2 Bit 1 T3M3 T3M2 T3M1 T3M3 T imer 3 M ode select bit 3 T3M2 T imer 3 M ode select bit 2 T3M1 T ...
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Timer 3 Control Register 1 (T3C) Write Timer 3 Status Register 1 (T3ST) Read 4551C–4BMCU–01/04 Bit 3 Bit 2 Write T3EIM T3TOP T3EIM T imer 3 E dge I nterrupt M ask T3EIM = 0, disables the interrupt when an ...
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Timer 3 Clock Select Register (T3CS) Timer 3 Compare- and Compare-mode Register T48C862-R4 [Preliminary] 64 Bit 3 Bit 2 T3CS T3E1 T3E0 T3E1 T imer 3 E dge select bit 1 T3E0 T imer 3 E dge select bit 0 ...
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Timer 3 Compare-Mode Register 1 (T3CM1) Timer 3 Compare Mode Register 2 (T3CM2) 4551C–4BMCU–01/04 Bit 3 Bit 2 T3CM1 T3SM1 T3TM1 T3SM1 T imer 3 S ingle action M ask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 ...
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Timer 3 COmpare Register 1 (T3CO1) Byte Write Timer 3 COmpare Register 2 (T3CO2) Byte Write Timer 3 Capture Register Timer 3 CaPture Register (T3CP) Byte Read T48C862-R4 [Preliminary] 66 Second write cycle Bit 7 First write cycle Bit 3 ...
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Synchronous Serial Interface (SSI) SSI Features: SSI Peripheral Configuration 4551C–4BMCU–01/04 • With Timer 1 – 2- and 3-wire NRZ – 2-wire mode multi-chip link mode (MCL), additional internal 2-wire link for multi-chip packaging solutions • With Timer 2 – Biphase ...
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General SSI Operation T48C862-R4 [Preliminary] 68 Figure 64. Block Diagram of the Synchronous Serial Interface SIC1 SC TOG2 SO POUT /2 T1OUT SYSCL Shift_CL Transmit Buffer The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit ...
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Synchronous Mode 4551C–4BMCU–01/04 Before data can be transferred, the SSI must first be activated. This is performed by means of the SSI reset control (SIR) bit. All further operation then depends on the data directional mode (TX/RX) and the ...
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T48C862-R4 [Preliminary] 70 Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the present contents of the shift register into the receive buffer. This can be used for clocking in a data telegram ...
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Shift Mode (MCL) 4551C–4BMCU–01/04 In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e always generated and output by the SSI. Both ...
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Pseudo MCL Mode MCL Bus Protocol T48C862-R4 [Preliminary] 72 Figure 69. Example of MCL Receive Dialog Start SC msb data 1 SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = ...
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Figure 70. MCL Bus Protocol 1 (1) ( Start Data condition valid Bus not busy (1) Both data and clock lines remain HIGH. Start data transfer (2) A HIGH to LOW transition of the SD line while ...
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SSI Interrupt Modulation and Demodulation T48C862-R4 [Preliminary] 74 The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e., transmit buffer empty or receive buffer full), the end of SSI data telegram or on the fall- ...
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Serial Interface Registers Serial Interface Control Register 1 (SIC1) 4551C–4BMCU–01/04 Bit 3 Bit 2 Bit 1 Bit 0 SIR SCD SCS1 SCS0 SIR S erial I nterface R eset SIR = 1, SSI inactive SIR = 0, SSI active SCD ...
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Serial Interface Control Register 2 (SIC2) T48C862-R4 [Preliminary] 76 Bit 3 Bit 2 Bit 1 MSM SM1 SM0 MSM M odular S top M ode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, modulator stop ...
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Serial Interface Status and Control Register (SISC) Serial Transmit Buffer (STB) – Byte Write 4551C–4BMCU–01/04 Bit 3 Bit 2 Write MCL RACK Read – TACK MCL M ulti- C hip L ink activation MCL = 1,multi-chip link disabled. This bit ...
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Serial Receive Buffer (SRB) – Byte Read Combination Modes Combination Mode Timer 2 and SSI Figure 73. Combination Timer 2 and SSI T2I SYSCL CL2/1 T1OUT TOG3 SCL RES T2C I/O-bus T48C862-R4 [Preliminary] 78 First read cycle Bit 7 Bit ...
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Combination Mode 1: Burst Modulation Combination Mode 2: Biphase Modulation 1 4551C–4BMCU–01/04 SSI mode 1: 8-bit NRZ and internal data SO output to the Timer 2 modulator stage Timer 2 mode 8-bit compare counter with ...
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Combination Mode 3: Manchester Modulation 1 Combination Mode 4: Manchester Modulation 2 T48C862-R4 [Preliminary] 80 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 8-bit ...
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Combination Mode 5: Biphase Modulation 2 4551C–4BMCU–01/04 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 2 modulator stage Timer 2 mode 3: 8-bit compare counter and 4-bit prescaler Timer 2 output mode 4: The modulator ...
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Combination Mode Timer 3 and SSI Figure 79. Combination Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 T1OUT SYSCL Combination Mode 6: FSK Modulation T48C862-R4 [Preliminary] 82 I/O-bus CP3 T3CP 8-bit counter 3 ...
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Combination Mode 7: Pulse-width Modulation (PWM) Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation 4551C–4BMCU–01/04 SSI mode 1: 8-bit shift register internal data output (SO) to the Timer 3 Timer 3 mode 9: Pulse-width modulation with the shift register data (SO) The ...
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Combination Mode 9: Biphase Demodulation T48C862-R4 [Preliminary] 84 Figure 82. Manchester Demodulation Timer 3 Synchronize mode T3I T3EX SI CM31=SCI SR-DATA Bit 7 SSI mode 1: 8-bit shift register internal data input (SI) and the internal shift ...
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Combination Mode Timer 2 and Timer 3 Figure 84. Combination Timer 3 and Timer 2 T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit counter 2/1 T1OUT SCL RES Compare 2/1 T2C I/O-bus ...
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Combination Mode 11: Burst Modulation 1 Figure 87. Burst Modulation 1 CL3 ...
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Combination Mode Timer 2, Timer 3 and SSI Figure 88. Combination Timer 2, Timer 3 and SSI T3CS T3I T3EX SYSCL CL3 8-bit Counter 3 T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit Counter 2/1 T1OUT SCL ...
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Combination Mode 12: Burst Modulation 2 Figure 89. Burst Modulation 2 CL3 ...
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Data EEPROM 4551C–4BMCU–01/04 Figure 90. FSK Modulation T3R Counter 3 CM31 CM32 0 SO T3O The internal data EEPROM offers 2 pages of 512 bits each. ...
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Serial Interface Serial Protocol T48C862-R4 [Preliminary] 90 The EEPROM uses a two-wire serial interface (TWI) to the microcontroller for read and write accesses to the data considered slave in all these applications. That means, the ...
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Control Byte Format EEPROM EEPROM – Operating Modes Write Operations Acknowledge Polling Write One Data Byte Write Two Data Bytes Write Control Byte Only 4551C–4BMCU–01/04 EEPROM Address Start Start Control byte Ackn Data byte The EEPROM has ...
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Write Control Bytes Read Operations Read One Data Byte Read Two Data Bytes Read n Data Bytes T48C862-R4 [Preliminary] 92 MSB Write low byte first A4 Byte order LB(R) MSB Write high byte first A4 Byte order HB(R) A -> ...
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Read Control Bytes Initialization the Serial Interface to the EEPROM 4551C–4BMCU–01/04 Read low byte first, A4 address increment Byte order LB(R) HB(R) Read high byte first, A4 address decrement Byte order HB(R) LB(R) A -> acknowledge, N -> no acknowledge; ...
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Absolute Maximum Ratings: Microcontroller Block Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those ...
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DC Operating Characteristics (Continued - +125 C unless otherwise specified. SS amb Parameters Power-on Reset Threshold Voltage POR threshold voltage POR threshold voltage POR hysteresis Voltage Monitor Threshold Voltage VM high threshold ...
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AC Characteristics Supply voltage V = 1 Parameters Operation Cycle Time System clock cycle Timer 2 input Timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time Timer ...
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AC Characteristics (Continued) Supply voltage V = 1 Parameters 32-kHz Crystal Oscillator (Operating Range V Frequency Start-up time Stability Integrated input/output capacitances (configurable) External 32-kHz Crystal Parameters Crystal frequency Serial resistance Static capacitance Dynamic capacitance ...
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Emulation Figure 94. MARC4 Emulation MARC4 emulator Program memory Trace memory Control logic Personal computer T48C862-R4 [Preliminary] 98 The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the ...
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Option Settings for Ordering Please select the option settings from the list below and insert ROM CRC. Output Port 1 BP10 [ ] CMOS [ ] Switched pull- Open drain [ Switched pull-down [ ] Open ...
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Ordering Information (1) Extended Type Number T48C862x-Rf-TNQ T48C862x-Rf-TNS Note Hardware revision frequency range = 3 (315 MHz (433 MHz (868 MHz/915 MHz) Package Information Package SSO24 Dimensions in mm 0.25 ...
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Table of Contents 4551C–4BMCU–01/04 Features................................................................................................. 1 Description ............................................................................................ 1 Pin Configuration.................................................................................. 2 Pin Description: RF Part ...................................................................... 2 Pin Description: Microcontroller Part ................................................. 3 UHF ASK/FSK Transmitter Block ........................................................ 4 Features................................................................................................. 4 Description ............................................................................................ 4 General Description.............................................................................. 6 Functional Description......................................................................... ...
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T48C862-R4 [Preliminary] 102 Components of MARC4 Core ............................................................ 14 Program Memory ................................................................................................ 14 RAM.................................................................................................................... 15 Expression Stack ..........................................................................................15 Return Stack .................................................................................................15 Registers............................................................................................................. 16 Program Counter (PC) ..................................................................................16 RAM Address Registers ................................................................................17 Expression Stack Pointer (SP) ......................................................................17 Return Stack Pointer (RP) ...
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Peripheral Modules............................................................................. 30 Addressing Peripherals....................................................................................... 30 Bi-directional Ports............................................................................. 33 Bi-directional Port 1 ............................................................................................ 33 Bi-directional Port 2 ............................................................................................ 34 Port 2 Data Register (P2DAT) ......................................................................35 Port 2 Control Register (P2CR) ....................................................................35 Bi-directional Port 5 ............................................................................................ 35 Port 5 Data ...
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T48C862-R4 [Preliminary] 104 Features ........................................................................................................54 Timer/Counter Modes ......................................................................................... 55 Timer 3 – Mode 1: Timer/Counter .................................................................56 Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) ...............................................57 Timer 3 – Mode 3: Timer/Counter, Internal Trigger ...
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Serial Interface Control Register 2 (SIC2) ....................................................76 Serial Interface Status and Control Register (SISC) .....................................77 Serial Transmit Buffer (STB) – Byte Write ....................................................77 Serial Receive Buffer (SRB) – Byte Read .....................................................78 Combination Modes ........................................................................... 78 Combination Mode Timer 2 ...
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T48C862-R4 [Preliminary] 106 Thermal Resistance............................................................................ 94 DC Operating Characteristics............................................................ 94 AC Characteristics.............................................................................. 96 Crystal Characteristics....................................................................... 97 Emulation............................................................................................................ 98 Option Settings for Ordering ............................................................. 99 Ordering Information........................................................................ 100 Package Information ........................................................................ 100 Table of Contents ............................................................................. 101 4551C–4BMCU–01/04 ...
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