T48C862M-R4-TNS Atmel, T48C862M-R4-TNS Datasheet - Page 65

• Manufacturer Part Number: T48C862M-R4-TNS
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNS

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Timer 3 Compare-Mode
Register 1 (T3CM1)
Timer 3 Compare Mode
Register 2 (T3CM2)
4551C–4BMCU–01/04
T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1
T3CM2 contains the mask bits for the match event of Counter 3 compare register 2
The compare registers and corresponding counter reset masks can be used to program
the counter time intervals and the toggle masks can be used to program output signal.
The single-action mask can also be used in this mode. It starts operating after the timer
started with T3R.
T3CM1
T3SM1
T3TM1
T3RM1
T3IM1
T3CM2
T3SM2
T3TM2
T3RM2
T3IM2
T imer 3 S ingle action M ask bit 1
T3SM1 = 0, disables single-action compare mode
T3SM1 = 1, enables single-compare mode. After this bit is set, the compare
T imer 3 compare T oggle action M ask bit 1
T3TM1 = 0, disables compare toggle
T3TM1 = 1, enables compare toggle. A match of Counter 3 with the compare
T imer 3 R eset M ask bit 1
T3RM1 = 0, disables counter reset
T3RM1 = 1, enables counter reset. A match of Counter 3 with the compare
T imer 3 I nterrupt M ask bit 1
T3RM1 = 0, disables Timer 3 interrupt for T3CO1 register.
T3RM1 = 1, enables Timer 3 interrupt for T3CO1 register.
T imer 3 S ingle action M ask bit 2
T3SM2 = 0, disables single-action compare mode
T3SM2 = 1, enables single-compare mode. After this bit is set, the compare
T imer 3 compare T oggle action M ask bit 2
T3TM2 = 0, disables compare toggle
T3TM2 = 1, enables compare toggle. A match of Counter 3 with the compare
T imer 3 R eset M ask bit 2
T3RM2 = 0, disables counter reset
T3RM2 = 1, enables counter reset. A match of Counter 3 with the compare
T imer 3 I nterrupt M ask bit 2
T3RM2 = 0, disables Timer 3 interrupt for T3CO2 register.
T3RM2 = 1, enables Timer 3 interrupt for T3CO2 register.
T3SM1
T3SM2
Bit 3
Bit 3
register (T3CO1) is used until the next compare match.
register (T3CO1) toggles the output flip-flop (TOG3).
register (T3CO1) resets the Counter 3.
register (T3CO2) is used until the next compare match.
register (T3CO2) toggles the output flip-flop (TOG3).
register (T3CO2) resets the Counter 3.
T3TM1
T3TM2
Bit 2
Bit 2
T48C862-R4 [Preliminary]
T3RM1
T3RM2
Bit 1
Bit 1
Address: "B"hex - Subaddress: "2"hex
Address: "B"hex - Subaddress: "3"hex
T3IM1
T3IM2
Bit 0
Bit 0
Reset value: 0000b
Reset value: 0000b
65