T48C862M-R4-TNS Atmel, T48C862M-R4-TNS Datasheet - Page 43

• Manufacturer Part Number: T48C862M-R4-TNS
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNS

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Timer 1 Control Register 2
(T1C2)
Watchdog Control Register
(WDC)
4551C–4BMCU–01/04
* Bit 3 -> MSB, Bit 0 -> LSB
* Bit 3 -> MSB, Bit 0 -> LSB
Both these bits control the time interval for the watchdog reset.
Table 15. Watchdog Time Control Bits
T1BP
T1CS
T1IM
WDL
WDR
WDT1
WDT0
WDT1
Bit 3 *
Bit 3 *
WDL
0
0
1
1
–
WDT0
T imer 1 SUBCL B y P assed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
T imer 1 input C lock S elect
T1CS = 1, CL1 = SUBCL (see Figure 34 on page 41)
T1CS = 0, CL1 = SYSCL (see Figure 34 on page 41)
T imer 1 I nterrupt M ask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
W atch D og L ock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR bit has no
W atch D og R un and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
W atch D og T ime 1
W atch D og T ime 0
T1BP
0
1
0
1
WDR
Bit 2
Bit 2
effect. After the WDL bit is cleared, the watchdog is active until a
system reset or power-on reset occurs.
Divider
131072
16384
2048
512
WDT1
T1CS
Bit 1
Bit 1
Delay Time to Reset with
T48C862-R4 [Preliminary]
WDT0
T1IM
Bit 0
Bit 0
SUBCL = 32 kHz
15.625 ms
62.5 ms
0.5 s
4 s
Address: "7"hex - Subaddress: "9"hex
Address: "7"hex - Subaddress: "A"hex
Delay Time to Reset with
0.256 ms/0.512 ms
1.024 ms/2.048 ms
SYSCL = 2/1 MHz
65.5 ms/131 ms
8.2 ms/16.4 ms
Reset value: x111b
Reset value: 1111b
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