T48C862M-R4-TNQ Atmel, T48C862M-R4-TNQ Datasheet - Page 72

• Manufacturer Part Number: T48C862M-R4-TNQ
• Description: IC MON TIRE PRESS 433MHZ 24-SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R4-TNQ

• Frequency: 433MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

8-bit Pseudo MCL Mode
MCL Bus Protocol
72
T48C862-R4 [Preliminary]
Figure 69. Example of MCL Receive Dialog
In this mode, the SSI exhibits all the typical MCL operational features except for the
acknowledge bit which is never expected or transmitted.
The MCL protocol constitutes a simple 2-wire bi-directional communication highway via
which devices can communicate control and data information. Although the MCL proto-
col can support multi-master bus configurations, the SSI in MCL mode is intended for
use purely as a master controller on a single master bus system. So all reference to
multiple bus control and bus contention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge bit.
Normally the communication channel is opened with a so-called start condition, which
initializes all devices connected to the bus. This is then followed by a data telegram,
transmitted by the master controller device. This telegram usually contains an 8-bit
address code to activate a single slave device connected onto the MCL bus. Each slave
receives this address and compares it with its own unique address. The addressed
slave device, if ready to receive data, will respond by pulling the SD line low during the
9th clock pulse. This represents a so-called MCL acknowledge. The controller detecting
this affirmative acknowledge then opens a connection to the required slave. Data can
then be passed back and forth by the master controller, each 8-bit telegram being
acknowledged by the respective recipient. The communication is finally closed by the
master device and the slave device put back into standby by applying a stop condition
onto the bus.
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
SRDY
ACT
SDD
SIR
SD
SC
Write STB
(tx data 1)
Start
msb
7 6 5 4 3 2 1
tx data 1
lsb
0 A
msb
7 6 5 4 3 2 1 0 A
rx data 2
lsb
4551C–4BMCU–01/04
Stop
Read SRB
(rx data 2)