MF0MOU2101DA4,118 NXP Semiconductors, MF0MOU2101DA4,118 Datasheet
MF0MOU2101DA4,118
Specifications of MF0MOU2101DA4,118
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MF0MOU2101DA4,118 Summary of contents
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... Rev. 3.2 — 19 May 2009 171432 1. General description NXP Semiconductors has developed MIFARE MF0ICU2 - MIFARE Ultralight used with Proximity Coupling Devices (PCD) according to ISO/IEC 14443A (see “ISO/IEC”). The communication layer (MIFARE RF Interface) complies to parts 2 and 3 of the ISO/IEC 14443A standard. The MF0ICU2 is primarily designed for limited use applications such as public transportation, event ticketing and NFC Forum Tag Type 2 applications ...
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... NXP Semiconductors 1.2.1 Cascaded UID The anticollision function is based individual serial number called Unique IDentification. The UID of the MF0ICU2 is 7 bytes long and supports cascade level 2 according to ISO/IEC 14443-3. 1.3 Security • 3DES Authentication • Anti-cloning support by unique 7-byte serial number for each device • ...
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... NXP Semiconductors 3. Applications Public transport Event ticketing Prepaid applications Loyalty schemes NFC Forum Tag Type 2 Toy and amusement 4. Quick reference data [1][2][3] Table 1. Quick reference data Symbol Parameter f input frequency i C input capacitance i EEPROM characteristics t write cycle time cy(W) t retention time ...
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... NXP Semiconductors 6. Block diagram antenna Fig 2. Block diagram 7. Functional description 7.1 Block description The MF0ICU2 chip consists of the 1536-bit EEPROM, the RF-Interface and the Digital Control Unit. Energy and data are transferred via an antenna, which consists of a coil with a few turns directly connected to the MF0ICU2. No further external components are necessary ...
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... NXP Semiconductors 7.2 State diagram and logical states description The commands are initiated by the PCD and controlled by the Command Interpreter of the MF0ICU2. It handles the internal states (as shown in generates the appropriate response. For a correct implementation of an anticollision procedure please refer to the documents ...
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... NXP Semiconductors 7.3 Memory organization The 1536-bit EEPROM memory is organized in 48 pages with 32 bits each. In the erased state the EEPROM cells are read as a logical “0”, in the written state as a logical “1”. Table 3. Page address Decimal 7.3.1 UID/serial number The unique 7 byte serial number (UID) and its two Block Check Character Bytes (BCC) are programmed into the first 9 bytes of the memory ...
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... NXP Semiconductors 7.3.2 Lock bytes Lock bytes enable the user to lock parts of the complete memory area for writing. A Read from user memory area cannot be restricted via lock bytes functionality. For this, please refer to the authentication functionality, (see 7.3.3 OTP bytes OPT bytes are pre-set to all “0” after production. These bytes may be bit-wise modified by a WRITE command ...
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... NXP Semiconductors 7.5 Command set The ATQA and SAK are identical as for MF0ICU1 (see specification MIFARE 3 “MIFARE ISO/IEC 14443 PICC The MF0ICU2 comprises the following command set: 7.5.1 REQA The MF0ICU2 accepts the REQA command in Idle state only. The response is the 2-byte ATQA ...
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... NXP Semiconductors 7.5.8 COMPATIBILITY WRITE The COMPATIBILITY WRITE command was implemented to accommodate the established MIFARE PCD infrastructure. Even though 16 bytes are transferred to the MF0ICU2, only the least significant 4 bytes (bytes will be written to the specified address recommended to set the remaining bytes all ‘0’. ...
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... NXP Semiconductors 9. Abbreviations Table 5. Acronym ATQA BCC CBC CRC EEPROM NAK OTP PCD PICC REQA RF SAK UID WUPA 3DES 10. References [1] ISO/IEC — International Organization for Standardization/International Electrotechnical Commission [2] MIFARE Interface Platform Type Identification Procedure — Application note, BL-ID Doc. No.: 018413 [3] MIFARE ISO/IEC 14443 PICC Selection — Application note, BL-ID Doc ...
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... NXP Semiconductors 11. Revision history Table 6. Revision history Document ID Release date MF0ICU2_SDS_32 20090519 MF0ICU2_SDS_32 Product short data sheet PUBLIC Data sheet status Product short data sheet PUBLIC Rev. 3 — 19 May 2009 171432 MF0ICU2 MIFARE Ultralight C Change notice Supersedes - - © NXP B.V. 2009. All rights reserved. ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 13. Contact information For more information, please visit: For sales office addresses, please send an email to: MF0ICU2_SDS_32 Product short data sheet PUBLIC http://www.nxp.com salesaddresses@nxp.com Rev. 3 — 19 May 2009 171432 MF0ICU2 MIFARE Ultralight C © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 14. Tables [1][2][3] Table 1. Quick reference data Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . .6 15. Figures Fig 1. MIFARE card reader . . . . . . . . . . . . . . . . . . . . . . .1 Fig 2. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 3. State diagram Fig 4. UID/serial number . . . . . . . . . . . . . . . . . . . . . . . . .6 MF0ICU2_SDS_32 Product short data sheet PUBLIC . . . . . . . . . . . . . . . . .3 Table 4. Table 5. Table 6. Rev. 3 — 19 May 2009 ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Contactless energy and data transfer 1.2 Anticollision 1.2.1 Cascaded UID . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 MIFARE‚ RF interface (ISO/IEC 14443 2.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 7 ...