XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet
XR20M1172IL32-F
Specifications of XR20M1172IL32-F
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XR20M1172IL32-F Summary of contents
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JUNE 2009 GENERAL DESCRIPTION 1 The XR20M1172 (M1172 high performance two channel universal asynchronous transmitter (UART) with 64 byte TX and RX FIFOs 2 and a selectable I C/SPI slave interface. The M1172 operates from 1.62 to 3.63 ...
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... TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO IGURE IN UT SSIGNMENT CTSA# GPIO4/DSRA# GPIO6/CDA# GPIO7/RIA# A0/CS# A1/SI SEL_I2C_SPI# VCC A0/CS# A1/ SI I2C/SPI# SO SDA RXB RXA TXA TXB XTAL1 XTAL2 GPIO2/CDB# GND ORDERING INFORMATION ART UMBER XR20M1172IL32 32-pin QFN XR20M1172IG28 28-Lead TSSOP 32-pin QFN 29 VCC XTAL2 28-Pin TSSOP ...
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REV. 1.0.1 PIN DESCRIPTIONS Pin Description 32-QFN 28-TSSOP N AME I2C (SPI) INTERFACE SDA RXB 5 8 RXA 6 9 TXA 7 10 TXB 9 11 XTAL1 ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO Pin Description 32-QFN 28-TSSOP N AME CTSB SCL 17 19 ENIR EN485 IRQ RTSA GPIO5/DTRA# 22 ...
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REV. 1.0.1 Pin Description 32-QFN 28-TSSOP N AME GPIO7/RIA VCC 29 1 A0/CS A1/ I2C/SPI PAD - Pin type: I=Input, O=Output, ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR20M1172 (M1172) integrates a selectable I Universal Asynchronous Receiver and Transmitter (UART). The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each ...
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REV. 1.0.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The M1172 can operate with either an I the I2C/SPI# input pin. 2 2.1.1 I C-bus Interface 2 The I C-bus interface is compliant with the Standard-mode and Fast-mode I bus interface ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO IGURE ATA ORMATS SLAVE Master write: ADDRESS START condition write acknowledge SLAVE Master read: ADDRESS START condition read acknowledge ...
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REV. 1.0.1 2 2.1.1.1 I C-bus Addressing There could be many devices on the I are eight possible slave addresses that can be selected for the M1172 using the A1 and A0 address lines. Table 1 below shows the different ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.1.2 SPI Bus Interface The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input (SI). The serial clock, slave output and slave input ...
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REV. 1.0.1 The 64 byte TX FIFO can be loaded with data or 64 byte RX FIFO data can be unloaded in one SPI write or read sequence SPI FIFO W IGURE RITE ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO The IRQ# interrupt output changes according to the operating mode and enhanced features setup. and 5 summarize the operating behavior for the transmitter and receiver. Also see T ABLE Auto RS485 Mode ...
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REV. 1.0.1 2.5 Crystal Oscillator or External Clock Input The M1172 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO When using 4X sampling mode, the bit time will have a jitter of ± 1/8 whenever DLD is non-zero, odd and not a multiple of 4. When using a non-standard data rate ...
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REV. 1.0 ABLE YPICAL DATA RATES WITH A Required D IVISOR FOR Output Data 16x Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 10000 150 19200 78.125 25000 60 28800 52.0833 38400 39.0625 ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.7.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the ...
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REV. 1.0.1 2.8 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It verifies and ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 16 IGURE ECEIVER PERATION IN 16X Clock ( DLD[5:4] ) Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Data FIFO Receive Data ...
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REV. 1.0.1 the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re- asserted (LOW), indicating more data may be sent. F 17. A RTS CTS F IGURE UTO AND LOW ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.12 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M1172 ...
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REV. 1.0.1 2.14.2 Auto Address Detection Auto address detection mode is enabled when EFCR bit and EFR bit The desired slave address will need to be written into the XOFF2 register. The receiver will try to ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.15 Infrared Mode The M1172 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder ...
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REV. 1.0.1 2.16 Sleep Mode with Auto Wake-Up The M1172 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 2.17 Internal Loopback The M1172 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART ...
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REV. 1.0.1 3.0 UART INTERNAL REGISTERS The complete register set is shown below UART INTERNAL REGISTER ADDRESSES ABLE A DDRESS 0X00 RHR - Receive Holding Register THR - Transmit Holding Register 0X00 DLL - Divisor LSB 0X01 ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO . T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x00 RHR RD Bit-7 0x00 THR WR Bit-7 0x01 IER RD/WR ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDR AME RITE 0x0B IOState RD/WR Bit-7 0x0C IOIntEna RD/WR Bit-7 0x0D reserved - 0 0x0E IOControl RD/WR 0 0x0F EFCR ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger ...
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REV. 1.0.1 IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt (default). • Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details. IER[6]: RTS# ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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REV. 1.0.1 FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the ...
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REV. 1.0.1 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO MCR[2]: OP1# / TCR and TLR Enable OP1# is not available as an output pin on the M1172. But it is available for use during Internal Loopback Mode (MCR[4] = 1). In ...
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REV. 1.0.1 MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit) • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO LSR[7]: Receive FIFO Data Error Flag • Logic FIFO error (default). • Logic global indicator for the sum of all error bits in the RX FIFO. ...
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REV. 1.0.1 MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO 4.15 GPIO Direction Register (IODir) - Read/Write This register is used to program the direction of the GPIO pins. Bit-7 to bit-0 controls GPIO7 to GPIO0. • Logic 0 = set GPIO ...
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REV. 1.0.1 4.19 Extra Features Control Register (EFCR) - Read/Write EFCR[7]: IrDA mode This bit selects between the slow and fast IrDA modes. See complete details. • Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO DLD[5:4]: Sampling Rate Select These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will double if the 8X mode is selected and ...
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REV. 1.0.1 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, TCR, TLR and DLD to be modified. After modifying any enhanced bits, EFR bit-4 ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO REGISTERS DLM, DLL DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL IODir IOState IOIntEna IOCont EFCR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX OP2# ...
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REV. 1.0.1 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (32-QFN) Thermal Resistance (28-TSSOP) DC ELECTRICAL CHARACTERISTICS o o TA= -40 ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - UART CLOCK o Unless otherwise noted: TA=- YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK UART External Clock T External Clock Time Period ECLK F ...
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REV. 1.0.1 AC ELECTRICAL CHARACTERISTICS - I2C-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL f Operating frequency SCL T Bus free time between STOP and START BUF T START condition hold time HD;STA T START ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 21. SCL IGURE ELAY FTER ESET RESET# SCL 2 F 22 IGURE US IMING IAGRAM START Protocol condition ( SU;STA LOW SCL ...
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REV. 1.0 IGURE ODEM NPUT IN NTERRUPT SLAVE SDA W ADDRESS IRQ MODEM pin F 25. GPIO P I IGURE IN NTERRUPT SLAVE SDA W A ADDRESS IRQ# GPIOn TWO CHANNEL I2C/SPI ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 26 IGURE ECEIVE NTERRUPT Start bit RX D0 IRQ IGURE ECEIVE NTERRUPT LEAR SLAVE SDA W A ADDRESS IRQ ...
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REV. 1.0.1 AC ELECTRICAL CHARACTERISTICS - SPI-BUS TIMING SPECIFICATIONS o Unless otherwise noted: TA=- YMBOL T CS# HIGH to SO three-state time TR T CS# to SCL setup time CSS T CS# to SCL hold time ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 30. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R GPIOx F 31. SPI W MCR DTR O IGURE RITE TO CS# SCLK SI R/W ...
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REV. 1.0.1 F 32. SPI W THR C IGURE RITE TO LEAR CS# SCLK SI R GPIOx IRQ# F 33. R MSR C M IGURE EAD TO LEAR CS# SCLK SI R IRQ# ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO F 34. R IOS C IGURE EAD TATE TO LEAR CS# SCLK SI R IRQ# F 35. R RHR C RX INT IGURE EAD TO LEAR CS# SCLK ...
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REV. 1.0.1 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO ) mm INCHES ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (28 PIN TSSOP - 4 Seating Plane e Note: The control dimension is in millimeter. SYMBOL α ) ...
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... Added UART Channel B select to Table 3. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO GENERAL DESCRIPTION ................................................................................................ 1 A ............................................................................................................................................... 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR20M1172 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. S ABLE 4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 27 4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 27 4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 27 4.3 INTERRUPT ENABLE REGISTER (IER) - ...
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XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO TABLE OF CONTENTS...................................................................................................... III REV. 1.0.1 I ...