XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 26

• Manufacturer Part Number: XR20M1172IL32-F
• Description: IC UART FIFO I2C/SPI 64B 32QFN
• Manufacturer: Exar Corporation

Specifications of XR20M1172IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

0x0A
A
0x01
0x02
0x02
0x03
0x05
0x07
0x06
0x07
0x08
0x09
XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
.
0x00
0x00
0x04
0x06
DDR
RXLVL
TXLVL
T
N
MCR
IODir
RHR
MSR
THR
FCR
LCR
SPR
TCR
R
LSR
TLR
IER
ISR
ABLE
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR Resume
RD/WR RX Trig
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
Global
FIFOs
Select
Clock
Pres-
B
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-3
Bit-3
Bit-7
IT
0/
0/
0
0
-7
RI# Input
RX FIFO
IR Mode XonAny
RTS Int.
Enabled
Resume
RX Trig
Enable
Trigger
Set TX
THR &
Empty
FIFOs
Break
B
Bit-6
Bit-6
TSR
Bit-6
Bit-2
Bit-2
Bit-6
Bit-6
Bit-6
IT
0/
0/
-6
16C550 Compatible Registers
TX FIFO
Set Par-
Resume
Xoff Int.
RX Trig
Enable
Source
Trigger
Empty
DSR#
B
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Bit-1
Bit-1
Bit-5
Bit-5
Bit-5
INT
ity
IT
0/
0/
0/
0/
-5
TX FIFO
Lopback
Resume
Internal
Enable
Source
Trigger
Enable
RX Trig
26
Sleep
Break
Mode
Parity
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-4
Bit-4
Bit-0
Bit-0
Bit-4
Bit-4
Bit-4
INT
RX
IT
0/
0/
0/
-4
S
INT Out-
HADED BITS ARE ENABLED WHEN
Stat. Int.
Framing
Modem
Source
TX Trig
Enable
Enable
Enable
Enable
OP2#/
Mode
Parity
B
DMA
Error
Delta
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Halt
INT
put
RX
IT
-3
Stop Bits
TX FIFO
and TLR
Stat. Int.
RX Line
TX Trig
Enable
Source
Enable
Reset
Parity
B
Delta
Error
Bit-2
Bit-2
Bit-2
TCR
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Halt
INT
RI#
RX
IT
0/
-2
RX FIFO
Overrun
Source
Control
TX Trig
Enable
Length
Output
Empty
Reset
DSR#
RTS#
Word
B
Error
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Halt
INT
RX
TX
Int
IT
-1
RX Data
RX Data
Source
Control
Enable
Enable
Length
Output
TX Trig
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
EFR B
Halt
INT
Int.
IT
-0
IT
See
See
See
See
-4=1
LCR ≠ 0xBF
C
LCR[7]=0
REV. 1.0.1
OMMENT
Table 12
Table 13
Table 12
Table 13