XR17V354IB176-F Exar Corporation, XR17V354IB176-F Datasheet
XR17V354IB176-F
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XR17V354IB176-F Summary of contents
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SEPTEMBER 2010 GENERAL DESCRIPTION 1 The XR17V354 (V354 single chip 4-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V354 serves as a single lane PCIe bridge to 4 ...
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... CLKREQ# PERST# MPIO7 GND L M GND MPIO8 MPIO11 MPIO14 N MPIO9 MPIO12 MPIO15 TRST# P MPIO10 MPIO13 TCK TDO NC RESET# TDI GND R ORDERING INFORMATION ART UMBER ACKAGE XR17V354IB176-F 176-FPBGA Transparent Top View DSR2# GND RTS2# TMRCK NC NC CD2# DTR2# RX2 ENIR RI2# CTS2# ...
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REV. 1.0.1 PIN DESCRIPTIONS AME IN YPE PCIe SIGNALS CLK+ G4 CLK RX+ G1 RX- G2 CLKREQ PERST# L2 REXT H3 MODEM OR SERIAL I/O INTERFACE TX0 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART PIN DESCRIPTIONS AME IN YPE RX2 B9 RTS2 CTS2# C8 DTR2 DSR2# A7 CD2# B7 RI2# C7 TX3 N5 O RX3 R5 RTS3 CTS3# ...
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REV. 1.0.1 PIN DESCRIPTIONS AME IN YPE D3 E14 I/O D2 D15 I/O D1 E13 I/O D0 C15 I/O SEL G13 I/O INT D14 I/O PRES H14 MPIO SIGNALS MPIO0 C1 I/O MPIO1 D2 I/O MPIO2 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART PIN DESCRIPTIONS AME IN YPE MPIO10 P1 I/O MPIO11 M3 I/O MPIO12 N2 I/O MPIO13 P2 I/O MPIO14 M4 I/O MPIO15 N3 I/O EEPROM SIGNALS EECK P13 O EECS R14 ...
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REV. 1.0.1 PIN DESCRIPTIONS AME IN YPE TMRCK A10 EN485# C10 ENIR# B10 TEST0 F2 TEST1 B11 TEST2 A11 VCC33 D5, D9, E12, Pwr J12, M7 VCC33A K3 Pwr VCC33P B13, C13 Pwr VCC33B B14, B15 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART FUNCTIONAL DESCRIPTION The XR17V354 (V354) integrates the functions of four independent enhanced 16550 UARTs, a general purpose 16-bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550 UART compatible configuration ...
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REV. 1.0.1 1.0 XR17V354 INTERNAL REGISTERS The XR17V354 UART register set is very similar to the previous generation PCI UARTs. This makes the V354 software compatible with the previous generation PCI UARTs. Minimal changes are needed to the software driver ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of information (see “Section 1.2, EEPROM Interface” on page T 1: PCI L ABLE A DDRESS B T ...
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REV. 1.0 PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x10 31:14 RWR Memory Base Address Register (BAR0) 13:0 RO Claims an 16K address space for the memory mapped UARTs including the UARTs on the ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART T 1: PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x78 31:16 RO PME# support (PME# can be asserted from D3hot and D0) PCI Power Management 1.2 15:8 RO Next Capability ...
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REV. 1.0 PCI L ABLE A DDRESS B T ITS YPE O FFSET 0xB0 31:0 RO PCIe Capability Offset 0x30 - Link Status2/Control2 0xB4-0xFF 31:0 RO Not implemented or not applicable (return zeros) 0x100 31 Resource ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART Table 3 shows the Target Addresses available for programming into bits 7:0 of the 16-bit address word. All other Target Addresses are reserved and must not be used. T ABLE T A ARGET DDRESS ...
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REV. 1.0 XR17V354 UART ABLE FFSET DDRESS EMORY 0x0000 - 0x000F UART channel 0 Regs 0x0010 - 0x007F Reserved 0x0080 - 0x009A DEVICE CONFIGURATION REGISTERS 0x009B - 0x00FF Reserved 0x0100 - 0x01FF UART 0 – ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 1.4 Device Configuration Registers The Device Configuration Registers provide easy programming of general operating parameters to the V354 and for monitoring the status of various functions. These registers control or report on all 4 ...
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REV. 1.0 ABLE EVICE A [A7:A0] R DDRESS EGISTER Ox098 MPIOINV[15:8] Ox099 MPIOSEL[15:8] 0x09A MPIOOD[15:8] 0x09B Reserved ABLE EVICE A R DDRESS EGISTER - INTERRUPT (read-only) 0x0080 0x0083 0x0084-0x0087 TIMER (read/write) 0x0088-0x008B ANCILLARY1 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART INT0 [7:0] Channel Interrupt Indicator Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and bit [3] indicates channel 3. The upper four bits INT0[7:4] ...
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REV. 1.0.1 T ABLE Wake-up Indicator is cleared by reading the INT0 register. RXRDY and RXRDY Time-out is cleared by reading data in the RX FIFO. RX Line Status interrupt clears after reading the LSR register that is in the ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 16-Bit Timer/Counter Programmable Registers TIMERMSB Register Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 REGA [15:8] Register Reserved. TIMERCNTL [7:0] Register The bits [3:0] of this register are used to issue commands. The commands are self-clearing, ...
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REV. 1.0.1 TIMER OPERATION The following paragraphs describe the operation of the 16-bit Timer/Counter. The following conventions will be used in this discussion: ’N’ is the 16-bit value programmed in the TIMER MSB, LSB registers ■ ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART IGURE IMER UTPUT IN NE HOT AND START TIMER COMMAND ISSUED TIMER Output in One-Shot Mode < 'N' Clocks After 'P' TIMER Output in clocks Re-triggerable Mode Timer ...
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REV. 1.0.1 8X sampling rate. Transmit and receive data rates will double by selecting 8X. If using the 4XMODE, the corresponding bit in this register should be logic 0 Individual UART Channel 8X Clock Mode Enable Bit-7 Bit-6 Bit-5 Bit-4 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART The 8-bit SLEEP register enables each UART separately to enter Sleep mode. The SLEEP register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the ...
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REV. 1.0.1 1.4.7 REGB Register REGB[18](Read/Write Logic 0 (default) - Global interrupt enable. Interrupts to PCI host are enabled. Logic 1 - Global interrupt disable. Interrupts to PCI host are disabled. REGB[19](Read-Only) Logic 0 - EEPROM load is valid. Logic ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART There are 2 sets of 6 registers that select, control and monitor the 16 multipurpose inputs and outputs. Figure 8 shows the internal circuitry IGURE ULTIPURPOSE NPUT UTPUT M ...
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REV. 1.0.1 MPIOINT [15:0] (default 0x00) The MPIOINT register enables the multipurpose input pin interrupt MPIO pin is selected by MPIOSEL as an input, then it can be selected to generate an interrupt. MPIOINT bit[0] enables input pin ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART MPIOSEL [15:0](default 0xFF) The MPIOSEL register defines the MPIOs as either an input or output. A logic 1 (default) defines the pin for input and a logic 0 for output. Bit-7 Bit-6 Bit-5 Bit-4 ...
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REV. 1.0.1 2.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each UART channel as shown ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART Channel Receive Data in 32-bit alignment through the Configuration Register Address Receive Data Byte n ...
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REV. 1.0.1 Channel Transmit Data in 32-bit alignment through the Configuration Register Address Transmit Data Byte n PCI Bus Data Bit-31 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 3.0 UART There are 4 UARTs channel [3:0] in the V354. Each has its own 256-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate ...
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REV. 1.0 IGURE AUD ATE ENERATOR 125 MHz Clock (Master) or 62.5 MHz Clock (Slave) HIGH PERFORMANCE QUAD PCI-EXPRESS UART To Other Channels DLL, DLM and DLD Registers MCR Bit-7=0 Prescaler (default) Divide by 1 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART T 11: T ABLE YPICAL DATA RATES WITH R D EQUIRED IVISOR FOR O D 16x Clock O UTPUT ATA R (Decimal) ATE 2400 3255.21 4800 1627.60 9600 813.80 10000 781.25 19200 406.90 25000 ...
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REV. 1.0.1 T 12: T ABLE YPICAL DATA RATES WITH R D EQUIRED IVISOR FOR O D 16x Clock O UTPUT ATA R (Decimal) ATE 2400 1627.60 4800 813.80 9600 406.90 10000 390.63 19200 203.45 25000 156.25 28800 135.63 38400 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 3.2 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# ...
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REV. 1.0.1 F 10. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 3.3 Infrared Mode Each UART in the V354 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.1. The input pin ENIR conveniently activates all 4 UART channels to ...
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REV. 1.0.1 3.4 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit [ logic 1. All regular UART functions operate normally. Figure 12 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 3.5 UART CHANNEL CONFIGURATION REGISTERS Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 ...
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REV. 1.0.1 T 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE RHR R BIT [ THR W BIT ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART T 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE EFR R/W Auto CTS/ DSR Enable Enable ...
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REV. 1.0 IGURE RANSMITTER PERATION IN NON ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 3.7 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit ...
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REV. 1.0.1 3.7.2 Receiver Operation with FIFO F 16 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 256 bytes by 11-bits wide FIFO Receive Data Receive Data Byte and Errors 3.7.3 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 4.0 UART CONFIGURATION REGISTERS 4.1 Receive Holding Register (RHR) - Read only SEE”RECEIVER” ON PAGE 44. 4.2 Transmit Holding Register (THR) - Write only SEE”TRANSMITTER” ON PAGE 42. 4.3 Baud Rate Generator Divisors (DLM, ...
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REV. 1.0.1 4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0] enables the XR16V354 in the FIFO polled mode of operation. Since the receiver and transmitter ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART IER[1]: TX Ready Interrupt Enable In non-FIFO mode interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is issued twice: once when the number of bytes in ...
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REV. 1.0.1 • Wake-up indicator is cleared by a read to the INT0 register ABLE P ISR R RIORITY EGISTER L B [5] B [4] B [3] EVEL ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are not available in this device provided for legacy software compatibility. • Logic 0 = Set DMA to ...
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REV. 1.0.1 T 16: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER T BIT [7] BIT [6] BIT [7] ABLE Table Table 4.7 Line Control Register (LCR) - Read/Write The ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART LCR BIT [5] LCR BIT [ LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit [3] set to a logic 1, LCR bit ...
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REV. 1.0.1 MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1) • Logic 0 = Divide by one. The internal 125MHz clock (master) or 62.5MHz clock (slave) is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode) DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by EFR ...
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REV. 1.0.1 LSR[3]: Receive Data Framing Error Flag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. ...
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REV. 1.0.1 T 18: A RS485 H ABLE UTO ALF MSR[7] MSR[ MSR [3]: Transmitter Disable This bit can be used to disable the ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART MSR [2]: Receiver Disable This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a logic 1, the receiver will operate in ...
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REV. 1.0.1 FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. RTS# or DTR# can be selected as the control output via MCR bit-2. Note that this feature has precedence over the Auto RTS/DTR flow control feature (EFR bit-6). ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 4.14 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bits [3:0] provide single or dual consecutive character software flow control selection (see are selected, the double 8-bit ...
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REV. 1.0.1 EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits, as shown in T ABLE EFR BIT [3] EFR BIT [2] EFR BIT [ ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 4.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write Only An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0xFF (255). The RX FIFO trigger level generates ...
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REV. 1.0.1 REGISTERS RESET STATE DLL Bits [7:0] = 0x01 DLM Bits [7:0] = 0x00 DLD Bits [7:0] = 0x00 RHR Bits [7:0] = 0xXX THR Bits [7:0] = 0xXX IER Bits [7:0] = 0x00 FCR Bits [7:0] = 0x00 ...
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XR17V354 HIGH PERFORMANCE QUAD PCI-EXPRESS UART ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (176-FPBGA) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O O TA=-40 + INDUSTRIAL GRADE S ...
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REV. 1.0.1 PACKAGE DIMENSIONS (176-FPBGA) D Seating Plane Note: The control dimension is the millimeter column OTE SYMBOL HIGH PERFORMANCE QUAD PCI-EXPRESS UART ...
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... September 2010 Rev 1.0.1 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...