XR17V354IB176-F Exar Corporation, XR17V354IB176-F Datasheet - Page 19

• Manufacturer Part Number: XR17V354IB176-F
• Description: IC UART PCIE 256B DUAL 176FPBGA
• Manufacturer: Exar Corporation

Specifications of XR17V354IB176-F

• Number Of Channels: 4, QUART
• Package / Case: 176-LFBGA
• Features: *
• Fifo's: 256 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 25 Mbps
• Supply Current: 120 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 176
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
The XR17V354 has a general purpose 16-bit timer/counter. The internal 125MHz clock (master mode) or
62.5MHz clock (slave mode) or the external clock at the TMRCK input pin can be selected as the clock source
for the timer/counter. The timer can be set to be a single-shot for a one-time event or re-triggerable for a
periodic signal. An interrupt may be generated when the timer times out and will show up as a Channel 0
interrupt (see
TIMERMSB]. The TIMERCNTL register provides the Timer commands such as start/stop, as shown in
below. The time-out output of the Timer can also be optionally routed to the MPIO[0] pin. The block diagram of
the Timer/Counter circuit is shown below:
TIMERMSB [31:24] and TIMERLSB [23:16] registers
The concatentaion of the 8-bit registers TIMERMSB and TIMERLSB forms a 16-bit value which decides the
time-out period of the Timer, per the following equation:
The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Notice that these registers do not hold the current counter value when read. Default value is zero
(timer disabled) upon powerup and reset. The ’Reset Timer’ command does not have any effect on this
register.
Wake-up Indicator is cleared by reading the INT0 register.
RXRDY and RXRDY Time-out is cleared by reading data in the RX FIFO.
RX Line Status interrupt clears after reading the LSR register that is in the UART channel register set.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel reg-
ister set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
1.4.2
F
IGURE
COMMANDS
TIMERCNTL
125MHz/62.5MHz
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (
0
X
TIMERMSB and TIMERLSB
XX-XX-00-00)
5. T
Table
Timer output frequency = Timer input clock / 16-bit Timer value
IMER
TMRCK
(16-bit Value)
7). It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB,
/C
Clock Select
Start/Stop
Single shot/Re-triggerable
Route/De-route to MPIO[0]
Timer Interrupt Enable/ Disable
OUNTER CIRCUIT
T
ABLE
1
0
8: UART C
Timer/Counter
HANNEL
16-Bit
19
[3:0] I
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
Timer Interrupt
NTERRUPT
MPIOLVL[0]
Output
Timer
1
0
C
LEARING
MPIO[0]
1
0
Timer Interrupt
No Interrupt
XR17V354
DEFAULT
Table 9