PK40X256VMD100 Freescale Semiconductor, PK40X256VMD100 Datasheet - Page 28

• Manufacturer Part Number: PK40X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: YES
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
1. The startup time is defined as the time between the IRC being enabled, either by the MCG or by the IRCLKEN bit being
2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification was obtained at TBD frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
28
Symbol
Symbol
J
J
t
pll_lock
set, and the first edge of the internal reference clock.
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
D
acc_pll
cyc_pll
D
each PCB and results will vary.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
V
lock
DD
unl
dco_t
) over voltage and temperature should be considered.
PLL period jitter (RMS)
PLL accumulated jitter over 1µs (RMS)
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Supply voltage
Description
Description
• f
• f
• f
• f
vco
vco
vco
vco
= 48 MHz
= 100 MHz
= 48 MHz
= 100 MHz
Table 16. Oscillator DC electrical specifications
K40 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 15. MCG specifications (continued)
Table continues on the next page...
Preliminary
± 1.49
± 4.47
1.71
Min.
Min.
—
—
—
—
—
1350
Typ.
Typ.
120
600
50
—
—
—
—
1075(1/
± 2.98
± 5.97
0.15 +
f
Max.
pll_ref
Max.
3.6
—
—
—
—
Freescale Semiconductor, Inc.
)
Unit
Unit
ms
ps
ps
ps
ps
%
%
V
Notes
Notes
10
10
11