PK40X256VMD100 Freescale Semiconductor, PK40X256VMD100 Datasheet - Page 44

• Manufacturer Part Number: PK40X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: YES
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
6.6.3 12-bit DAC electrical characteristics
6.6.3.1 12-bit DAC operating requirements
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
44
Symbol
V
V
DACR
T
C
0.18
0.16
0.14
0.12
0 08
0.08
0.06
0.04
0.02
DDA
I
L
A
0.1
L
0
0.1
Supply voltage
Reference voltage
Temperature
Output load capacitance
Output load current
Desciption
Figure 14. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
0.4
Table 30. 12-bit DAC operating requirements
K40 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
0.7
1
1.3
Preliminary
Vin level (V)
1.6
1.9
1.71
1.13
Min.
−40
—
—
2.2
Max.
105
100
3.6
3.6
2.5
1
Freescale Semiconductor, Inc.
2.8
Unit
mA
pF
°C
V
V
3.1
Notes
HYSTCTR
Setting
1
2
00
01
10
10
11