PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 28

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification was obtained at TBD frequency.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
10. This specification was obtained at internal frequency of TBD.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
28
Symbol
Symbol
I
t
DDOSC
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
each PCB and results will vary.
D
D
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
V
lock
DD
unl
dco_t
) over voltage and temperature should be considered.
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Supply voltage
Supply current — low-power mode (HGO=0)
Description
Description
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
Table 14. Oscillator DC electrical specifications
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 13. MCG specifications (continued)
Table continues on the next page...
Preliminary
± 1.49
± 4.47
1.71
Min.
Min.
—
—
—
—
—
—
—
Typ.
Typ.
500
200
300
700
1.2
1.5
—
—
—
—
1075(1/
± 2.98
± 5.97
0.15 +
f
Max.
pll_ref
Max.
3.6
—
—
—
—
—
—
Freescale Semiconductor, Inc.
)
Unit
Unit
mA
mA
ms
μA
μA
μA
nA
%
%
V
Notes
Notes
11
1