PK40N512VMD100 Freescale Semiconductor, PK40N512VMD100 Datasheet - Page 51

• Manufacturer Part Number: PK40N512VMD100
• Description: IC ARM CORTEX MCU 512K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40N512VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: Yes
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 128 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.6.3.2 12-bit DAC operating behaviors
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to V
3. The DNL is measured for 0+100 mV to V
4. The DNL is measured for 0+100mV to V
Freescale Semiconductor, Inc.
I
I
DDA_DACLP
t
t
DDA_DACH
V
Symbol
CCDACHP
V
CCDACLP
V
t
t
PSRR
DACHP
DACLP
OFFSET
dacouth
DNL
DNL
Rop
dacoutl
T
T
INL
BW
SR
E
CT
A
P
CO
GE
G
C
Supply current — low-power mode
Supply current — high-speed mode
Full-scale settling time (0x080 to 0xF7F) — low-
power mode
Full-scale settling time (0x080 to 0xF7F) — high-
power mode
Code-to-code settling time (0xBF8 to 0xC08) —
low-power mode
Code-to-code settling time (0xBF8 to 0xC08) —
high-speed mode
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
DAC output voltage range high — high-speed
mode, no load, DAC set to 0xFFF
Integral non-linearity error — high speed mode
Differential non-linearity error — V
Differential non-linearity error — V
VREFO (1.15 V)
Offset error
Gain error
Power supply rejection ratio, V
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
Output resistance load = 3 kΩ
Slew rate -80h→ F7Fh→ 80h
Channel to channel cross talk
3dB bandwidth
Description
• High power (SP
• Low power (SP
• High power (SP
• Low power (SP
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 30. 12-bit DAC operating behaviors
LP
LP
HP
HP
)
)
)
)
DACR
DDA
DACR
DACR
DACR
DACR
−100 mV
> = 2.4 V
−100 mV with V
−100 mV
> 2 V
=
Preliminary
DDA
V
−100
±0.4
±0.1
0.05
Min.
550
DACR
1.2
60
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
> 2.4V
Peripheral operating requirements and behaviors
TBD
TBD
TBD
0.12
Typ.
100
100
1.7
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
Max.
TBD
TBD
±0.8
±0.6
150
700
200
250
DACR
-80
30
±8
±1
±1
90
—
—
—
—
—
—
—
5
ppm of
%FSR
%FSR
FSR/C
μV/yr
μV/C
V/μs
LSB
LSB
LSB
Unit
kHz
mV
mV
μA
μA
dB
dB
μs
μs
μs
μs
Ω
Notes
1
1
1
1
2
3
4
5
5
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