EGLXT973QEA3V-873181 Cortina Systems Inc, EGLXT973QEA3V-873181 Datasheet - Page 74

• Manufacturer Part Number: EGLXT973QEA3V-873181
• Description: IC TXRX 2PORT ETH EXT 100-MQFP
• Manufacturer: Cortina Systems Inc

Specifications of EGLXT973QEA3V-873181

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1001

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Table 26
Cortina Systems
Special Function Register (Address 27)
®
Line Length Indication
Special Functions
1. Refer to
2. Register bits 27.11:10 are latched in from hardware pins on hardware reset.
27.15:13
27.11:10
27.3:0
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
27.12
27.9
27.8
27.7
27.6
27.5
27.4
Bit
Line Length
Indicator
Reserved
Per-Port Rise
time Control
Auto MDIX enable
Auto MDIX
Analog Loopback
Loopback Detect
Enable
Loopback Speed-
Up Enable
Loopback
Detected
Reserved
Table 15 on page 65
Name
111 = Longest
110 =
101 =
100 =
011 =
010 =
001 =
000 = Shortest
Write as 0, ignore on read
00 = 3.3 ns (default pins TxSLEW<1:0>)
01 = 3.6 ns
10 = 3.9 ns
11 = 4.2 ns
0 = Disable Auto-MDIX
1 = Enable Auto-MDIX
MDI/MDIX selection
1 = Enable Analog Loopback (transmits on twisted-
pair)
0 = Disable Analog Loopback
1 = Enable automatic loopback detection.
0 = Disable automatic loopback detection
1 = Enable automatic loopback detection speed-up
0 = Disable automatic loopback detection speed-up
1 = Loopback detected
0 = No loopback detected
Write as 0, ignore on read
0 = MDI, transmit on pair A and receive on pair B
1 = MDIX, transmit on pair B and receive on pair A
for Register Bit Descriptions.
Description
Approximate line-
length
corresponding to
each value will be
determined at
design verification
(Not valid when
agcset (Register
bit 30.13 = 1)
12.0 Register Definitions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
1
Default
Note 2
LHR
000
00
Page 74
0
1
1
0
0
0
0