EGLXT973QEA3V-873181 Cortina Systems Inc, EGLXT973QEA3V-873181 Datasheet - Page 86

• Manufacturer Part Number: EGLXT973QEA3V-873181
• Description: IC TXRX 2PORT ETH EXT 100-MQFP
• Manufacturer: Cortina Systems Inc

Specifications of EGLXT973QEA3V-873181

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1001

LXT973 Transceiver
Datasheet
249426, Revision 6.0
13 July 2007
Figure 34
Table 45
Cortina Systems
10BASE-T Receive Timing (Parallel Mode)
MII - 10BASE-T Receive Timing Parameters (Parallel Mode)
®
RXD, RXDV, RXER setup to
RXCLK High
RXD, RXDV, RXER hold from
RXCLK High
Twisted-pair input to RXD out (Rx
latency)
CRS asserted to RXD, RXDV,
RXER asserted
RXD, RXDV, RXER de-asserted
to CRS de-asserted
Twisted-pair input to CRS
asserted
Twisted-pair input quiet to CRS
de-asserted
Twisted-pair input to COL
asserted
Twisted-pair input quiet to COL
de-asserted
1. Typical values are at 25°C, and are for design aid only, are not guaranteed, and are not subject to
2. CRS is asserted. RXD/RXDV are driven at the start of SFD (64 BT) unless Register bit 16.5 is set.
3. If Register bit 16.7 is set, CRS extends to RXDV de-assert.
Note:
Twisted-Pair
LXT973 10/100 Mbps Dual-Port Fast Ethernet PHY Transceiver
production testing.
RXCLK
RXDV,
RXER
RXD,
Input
CRS
COL
Twisted-pair input default pins are as follows: DPBP/N_0 and DPAP/N_1.
Parameter
2
3
t
6
t
8
t
3
Sym
t1
t2
t3
t4
t5
t6
t7
t8
t9
t
4
Min
10
10
–
–
–
–
–
–
–
t
Typ
1
0.5
64
62
–
–
4
4
4
4
1
t
2
Max
–
–
–
–
–
–
–
–
–
Units
BT
BT
BT
BT
BT
BT
BT
ns
ns
15.0 Timing Diagrams
t
t
7
9
t
5
Conditions
–
Test
–
–
–
–
–
–
–
–
Page 86