WM8974GEFL/V Wolfson Microelectronics, WM8974GEFL/V Datasheet - Page 14

• Manufacturer Part Number: WM8974GEFL/V
• Description: Audio CODECs Mono Codec with Spkr
• Manufacturer: Wolfson Microelectronics

Specifications of WM8974GEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-24
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8974
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INPUT SIGNAL PATH
MICROPHONE INPUTS
The WM8974 can accommodate a variety of microphone configurations including single ended and
differential inputs.
through the input PGA as shown in Figure 6 .
A pseudo differential input is the preferential configuration where the positive terminal of the input
PGA is connected to the MICP input pin by setting MICP2INPPGA=1. The microphone ground
should then be connected to MICN (when MICN2INPPGA=1) or optionally to AUX (when
AUX2INPPGA=1) input pins.
Alternatively a single ended microphone can be connected to the MICN input with MICN2INPPGA set
to 1. The non-inverting terminal of the input PGA should be connected internally to VMID by setting
MICP2INPPGA to 0.
In differential mode the larger signal should be input to MICP and the smaller (e.g. noisy ground
connection) should be input to MICN.
CONTROL INTERFACES
To allow full software control over all its features, the WM8974 offers a choice of 2 or 3 wire MPU
control interface. It is fully compatible and an ideal partner for a wide range of industry standard
microprocessors, controllers and DSPs. The selection between 2-wire mode and 3-wire mode is
determined by the state of the MODE pin. If MODE is high then 3-wire control mode is selected, if
MODE is low then 2-wire control mode is selected.
In 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010.
CLOCKING SCHEMES
WM8974 offers the normal audio DAC clocking scheme operation, where 256fs MCLK is provided to
the DAC/ADC.
However, a PLL is also included which may be used to generate the internal master clock frequency
in the event that this is not available from the system controller. This PLL uses an input clock,
typically the 12MHz USB or ilink clock, to generate high quality audio clocks. If this PLL is not
required for generation of these clocks, it can be reconfigured to generate alternative clocks which
may then be output on the CSB/GPIO pin and used elsewhere in the system.
POWER CONTROL
The design of the WM8974 has given much attention to power consumption without compromising
performance. It operates at low supply voltages, and includes the facility to power off any unused
parts of the circuitry under software control, includes standby and power off modes.
The WM8974 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input. These
inputs can be used in a variety of ways. The input signal path before the ADC has a flexible PGA
block which then feeds into a gain boost/mixer stage.
The inputs through the MICN, MICP and optionally AUX pins are amplified
PD, Rev 4.5, September 2008
Production Data
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