PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 168

• Manufacturer Part Number: PIC18F6585-I/L
• Description: Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6585-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 48 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
14.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated up to 200 kHz. See Section 12.0
“Timer1 Module” for further details.
14.3
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to 0FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit, TMR3IE
(PIE2<1>).
TABLE 14-1:
DS30491C-page 166
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Name
Timer1 Oscillator
Timer3 Interrupt
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
RD16
RD16
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
GIEH
Bit 7
GIE/
—
—
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CCP2
PEIE/
CMIE
CMIP
CMIF
Bit 6
GIEL
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0
TMR0IE
Bit 5
—
—
—
INT0IE
EEIF
EEIE
EEIP
Bit 4
T3CCP1
BCLIE
BCLIP
BCLIF
RBIE
Bit 3
T3SYNC
TMR0IF
14.4
If the CCP module is configured in Compare mode
to
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
LVDIF
LVDIE
LVDIP
Bit 2
Note:
generate
Resetting Timer3 Using a CCP
Trigger Output
TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR3IF
TMR3IE
TMR3IP
INT0IF
Bit 1
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
a
CCP2IF
CCP2IE
CCP2IP
RBIF
Bit 0
 2004 Microchip Technology Inc.
“special
0000 0000 0000 0000
-0-0 0000 -0-0 0000
-0-0 0000 -0-0 0000
-1-1 1111 -1-1 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
event
Value on
all other
Resets
trigger”