PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 338

• Manufacturer Part Number: PIC18F6585-I/L
• Description: Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6585-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 48 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
23.9
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non-Return-
to-Zero (NRZ) coding which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission time may vary from
node to node, the receiver must have some type of
Phase Lock Loop (PLL) synchronized to data transmis-
sion edges to synchronize and maintain the receiver
clock. Since the data is NRZ coded, it is necessary to
include bit stuffing to ensure that an edge occurs at
least every six bit times to maintain the Digital Phase
Lock Loop (DPLL) synchronization.
The bit timing of the PIC18F6585/8585/6680/8680 is
implemented using a DPLL that is configured to syn-
chronize to the incoming data and provides the nominal
timing for the transmitted data. The DPLL breaks each
bit time into multiple segments made up of minimal
periods of time called the Time Quanta (T
Bus timing functions executed within the bit time frame,
such as synchronization to the local oscillator, network
transmission delay compensation, and sample point
positioning, are defined by the programmable bit timing
logic of the DPLL.
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different clock
frequencies of the individual devices, the bit rate has to
be adjusted by appropriately setting the baud rate
prescaler and number of time quanta in each segment.
The Nominal Bit Rate is the number of bits transmitted
per second, assuming an ideal transmitter with an ideal
oscillator, in the absence of resynchronization. The
nominal bit rate is defined to be a maximum of 1 Mb/s.
FIGURE 23-4:
DS30491C-page 336
Input
Signal
Bit
Time
Intervals
T
Baud Rate Setting
Q
Segment
BIT TIME PARTITIONING
Sync
Propagation
Segment
Q
).
Segment 1
Phase
Nominal Bit Time
The Nominal Bit Time is defined as:
EQUATION 23-1:
The Nominal Bit Time can be thought of as being
divided into separate, non-overlapping time segments.
These segments (Figure 23-4) include:
• Synchronization Segment (Sync_Seg)
• Propagation Time Segment (Prop_Seg)
• Phase Buffer Segment 1 (Phase_Seg1)
• Phase Buffer Segment 2 (Phase_Seg2)
The time segments (and thus the Nominal Bit Time) are
in turn made up of integer units of time called Time
Quanta or T
inal Bit Time is programmable from a minimum of 8 T
to a maximum of 25 T
Nominal Bit Time is 1 s, corresponding to a maximum
1 Mb/s rate. The actual duration is given by the
relationship:
EQUATION 23-2:
The Time Quantum is a fixed unit derived from the
oscillator period. It is also defined by the programmable
baud rate prescaler with integer values from 1 to 64 in
addition to a fixed divide-by-two for clock generation.
Mathematically, this is:
EQUATION 23-3:
where F
sponding oscillator period, and BRP is an integer (0
through 63) represented by the binary values of
BRGCON1<5:0>.
Nominal Bit Time = T
Sample Point
OSC
T
T
Q
Q
Q
is the clock frequency, T
( s) = (2 * (BRP+1))/F
(see Figure 23-4). By definition, the Nom-
( s) = (2 * (BRP+1)) * T
T
Phase_Seg1 + Phase_Seg2)
BIT
= 1/Nominal Bit Rate
Q
. Also by definition, the minimum
 2004 Microchip Technology Inc.
Q
Segment 2
* (Sync_Seg + Prop_Seg +
or
Phase
OSC
OSC
OSC
(MHz)
( s)
is the corre-
Q